PC87415VCG datasheet(22/42 Pages) NSC

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70 Functional Description (Continued)

7315 DMA Mode

This class includes the following commands

Read DMA

Write DMA

Data transfers using the DMA commands differ in two ways

from PIO transfers

Data transfers are performed using the built-in DMA en-

gine

No intermediate sector interrupts are issued on multi-

sector commands

The protocol is separated into 3 phases as follows

a Command phase

1 The CPU initializes the DMA engine in the device (see

Bus Master Operation section)

2 The CPU updates the command Block Registers

3 The CPU writes the command code to the Command

b Data phase

1 See DMA Engine Protocol section

c Status phase

1 The drive generates the interrupt to the CPU

2 The CPU issues a Stop command to the DMA engine

3 The CPU reads the Status Register and Error Register

TLF12497 – 7

732 Independent Timing per Drive

The device provides independent timings for reads writes

and commandcontrol cycles per channel and per drive on

each channel All command and control block accesses are

8 bits and use one timing register to control the timing pa-

rameters All accesses to the data register (offset 0) are

always 16 bits and use the timing registers 44h – 4Bh

Each drive on a channel has two separate timing controls

(one for read cycles and one for write cycles) A snooping

mechanism is used to switch between drives in a channel

After reset all accesses to channel 1 use ‘‘channel 1-device

1’’ timing and all accesses to channel 2 use ‘‘channel 2-de-

vice 1’’ timing When a command write to channel 1 with

offset address of 6 is issued with bit 4 set (DRV) the control-

ler will begin to use channel 1 device 2 timing for all succes-

sive accesses to that channel Writing to channel 1 with

offset of 6 with bit 4 cleared (DRV) will cause the controller

to use channel 1 device 1 timing This same mechanism is

used for channel 2 separately

733 Flow Control

7331 PIO

IORDY handshaking is provided for flow control between

the controller and the IDE drive when the device is in PIO

mode The IORDY handshaking is the current specified flow

control for PIO cycles in the ATA-2 specification

73311 IORDY

IORDY handshaking protocol is as follows

1 The device receives a readwrite datacommand ac-

cessing the drive

2 The device begins to generate IDE cycles using the tim-

ing associated with the channel number drive number

and cycle type (read write data or command)

3 Prior to completing the IDE cycle the device samples

DIORDY on the second to last clock of the cycle active

time (one clock prior to the clock cycle that would de-as-

sert the command) at which time the device either ex-

tends the cycle or completes depending on DIORDY

The cycle is extended as long as DIORDY is low (not

ready)

4 When DIORDY is sampled high the cycle is completed

Sample DIORDY

TLF12497 – 8

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