PC87415VCG datasheet(29/42 Pages) NSC

29 / 42 page

70 Functional Description (Continued)

74242 PCI Master Writes

When the device wants to transfer data from the drive into

memory it will request the PCI bus under the following con-

ditions

(prefetch buffer is full or half full) or ((CHx

INT) and ((EOT

is 0) or (byte count is not 0)))

The device will request the bus when the prefetch buffer is

full or half full or one of the channel generates an interrupt

while the DMA is still active (not EOT or byte count is not 0)

When the device is granted the PCI bus it will assert

FRAME

and write 2 Dwords (if the prefetch buffer is half

full) or 4 Dwords (if the prefetch buffer is full) to memory As

soon as the first Dword is written out to memory the read

prefetch buffer will no longer be full or half full so therefore

the PCI request will be deasserted until the read prefetch

buffer is written out to memory The device will keep assert-

ing FRAME

until all 4 Dwords are written to memory If the

device encounters a retry (STOP

asserted) while writing

the 2 or 4 Dwords it will release FRAME

and wait until the

read prefetch buffer is either full or half full again When the

prefetch buffer is full the device will request the PCI bus

and try to write 4 more Dwords to memory When the pre-

fetch buffer is half full the device will request the PCI bus

and try to write 2 or more Dwords to memory

Each Dword write cycle is first qualified with the DMA being

active or the prefetch buffer not empty The condition for

deasserting FRAME

is expressed by the following

(burst in 2 or 4 Dwords) or (prefetch buffer is empty) or

((EOT is 1) and (byte count is 0))

If the byte count was programmed to be less than the drive

transfer length the device will stop writing data out to mem-

ory as soon as byte count is 0 and will release the PCI bus

but will continue to prefetch from the drive because DMREQ

is still asserted (drive is not finished) The DMA controller

will then stop and walt for software to do something When

the software times out it will read the DMA status register

When the device sees a stop command and another start

command it will clear the contents of the prefetch buffers

743 Master Aborts

When a DMA channel is transferring data to a PCI target

and the target does not respond with DEVSEL

a master

abort condition occurs During master abort the following

actions are taken

1 Set bit 13 of Status register (07h) indicating that the

transaction was terminated by a master abort

2 Set the error bit in the Bus Master IDE status register for

the appropriate channel

3 Clear the Active bit in the Bus Master IDE status register

for the appropriate channel

4 Relinquish the PCI bus (de-assert REQ )

5 De-assert DMACK

to the IDE drive and stop IDE cy-

cles

6 Clear buffers of the appropriate channel

744 Target Aborts

When a DMA channel is transferring data to a PCI target

and the target issues a target abort the following actions are

taken

1 Set bit 12 of Status reg (07) indicating that the transac-

tion was terminated by a target abort

2 Set the error bit in the Bus Master IDE status register for

the appropriate channel

3 Clear the Active bit in the Bus Master IDE status register

for the appropriate channel

4 Relinqulsh the PCI bus (de-assert REQ )

5 De-assert DMACK

to the IDE drive and stop IDE cy-

cles

6 Clear buffers of the appropriate channel

745 Data Synchronization

The following is the protocol for data synchronization

i During DMA delay the interrupt from the IDE until the

FIFO is empty and the EOT e 1 and BC e 0

ii No retry cycles generated when reading the DMA status

registers (DMA status registers are always readable)

When the device is doing PCI master writes the device buff-

ers data from the drive using the prefetch buffers If an IDE

interrupt is encountered while the prefetch buffers are not

emptied the device delays the interrupt (INTA or IRQ14 or

IRQ15) until the FIFO is emptied and until EOT equals 1 and

Byte Count equals 0 This is done to ensure that when soft-

ware reads the status register of the device (caused by re-

ceiving an IDE interrupt) the device has already flushed the

prefetch buffers

There are four cases that need to be considered when soft-

ware reads the status register of the device normal byte

count is less than IDE transfer size byte count is greater

than IDE transfer size and transfer in progress

7451 Normal

In normal completion CHx

INT is delayed until the channel

x FIFO is empty and EOT equals 1 and Byte Count equals 0

The status register will indicate Channel x Interrupt bit set

and the Channel x Active bit set indicating a normal comple-

tion

7452 Byte Count is Less Than IDE Transfer Size

When the Byte Count is programmed to be less than the

IDE transfer size by more than 4 DWords an IDE interrupt

will not be generated and the software will time out When

the software reads the device’s status register it will see the

Channel x Interrupt bit not set and the Channel x Active bit

not set

When the Byte Count is programmed to be less than the

IDE transfer size by less than 4 DWords an IDE interrupt

will be received by the device but will be blocked because

the FIFO is not empty The software will time out because it

has not received any interrupt It will then read the status

Channel x Active bit not set This will be interpreted as an

error condition (even though the status register reads back

as normal completion) because no interrupt has been re-

ceived

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