PC87415VCG datasheet(24/42 Pages) NSC

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70 Functional Description (Continued)

735 Prefetching

The device has the ability to prefetch IDE data during reads

to the IDE data port (1F0 170 BAR0 offset 0 BAR2 offset

0) Since the CPU will always request data in sector blocks

(sector size is programmable) the device can initiate the

next read operation to the drive while the CPU is writing the

currently fetched data out to system memory The device

provides a sector count in order not to prefetch beyond the

sector boundary which could cause a fatal error on some

disks

If prefetch is enabled upon the detection of a read to the

IDE data port the device will begin prefetching Prefetching

will continue until either the sector count expires or the IDE

command register (offset 07) is loaded with the following

commands

E4h

Read buffer

C4h

Read multiple

20h

Read sector(s) (wretry)

21h

Read sector(s) (wo retry)

In either of these two cases prefetch will stop and the sec-

tor count re-loaded Prefetching will resume upon a detec-

tion of a read to the IDE data port and if the prefetch buffer

is not full If the sector is disrupted for any reason the sec-

tor counter will reset on the next read command in order

that reads will not pass the end of sector somewhere down

the line This is not normally a problem in PC-compatible

systems since the system will always transfer the entire

amount of data requested But for additional control these

read commands are monitored for synchronization

736 LegacyNative Mapping Scheme

The device indicates to the BIOS that it is an IDE device by

returning 01 in the Class code byte (indicating that it is a

mass storage controller) and a 01 in the Sub-Class code

byte (indicating that it is an IDE controller) of the Class Code

or native mode There is a pair of bits per IDE channel in the

Programming Interface register that indicate to the BIOS

which mode(s) the device supports Bits 0 and 1 of the Pro-

gramming Interface register correspond to channel 1 bits 2

and 3 correspond to channel 2 (see Programming Interface

When the device is programmed in legacy mode the device

will respond to the following addresses

Primary

1F0h – 1F7h 3F6h

Secondary 170h – 177h 376h

When channel 1 is in legacy mode the Base Address Reg-

isters 0 – 1 are not used and when channel 2 is legacy mode

Base Address Registers 2 – 3 are not used When in legacy

mode each channel can be disabled independently by soft-

ware To turn off a legacy channel software writes a one to

the mode bit of the Programming Interface register (bits 0 or

2) When a channel is in native mode it will not respond to

legacy addresses but will claim addresses defined by the

Base Address Register 0 – 1 for channel 1 and Base Ad-

dress Register 2 – 3 for channel 2

74 DMA CONTROLLER

The built-in DMA controller allows the IDE controller to

transfer data tofrom the IDE drive by becoming a PCI bus

master The DMA supports scattergather which provides

the capability of transferring multiple memory regions be-

tween system memory and the IDE drive without CPU inter-

vention The DMA controller can read the memory address

and word count from an array of region descriptors located

in system memory called the Physical Region Descriptor

Table This allows the DMA controller to sustain DMA trans-

fers until all the memory regions in the PRD Table are trans-

ferred The format of each entry in the Physical Region De-

scriptor Table is shown in Table III

TABLE III Physical Region Descriptor Table Entry

Byte 3

Byte 2

Byte 1

Byte 0

Memory Region Physical Base Address 311

EOT

Reserved

Byte Count 151

Each Physical Region Descriptor entry is 8 bytes in length

The PC87415 allows for 8192 table entries Table IV below

describes the descriptor in more detail The descriptor table

must be aligned on a 4 byte boundary and the table cannot

cross a 64k boundary in memory This limitation exists only

if the table in memory is not contiguous If the table crosses

a page boundary and that memory page is located in a dif-

ferent physical memory location the PC87415 does not

have the ability to gather the table from memory If the table

is contiguous in memory then the table could straddle a 64k

boundary

TABLE IV Physical Region Descriptor

Byte

Description

0 – 3

Bit 0 always 0

Bit 1–31 Memory Region Physical Base

Address (corresponds to AD 311 )

4 – 7

Bit 0 not used

Bit 1 – 15 Byte count

Bit 16 – 30 reserved

Bit 31 EOT

0 e There are more entries in the Physical

Region Descriptor table

1 e There are no more entries in the

Physical Region Descriptor table

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