PC87415VCG datasheet(28/42 Pages) NSC

28 / 42 page

70 Functional Description (Continued)

74232 Bus Master Reads

The device requests the PCI bus and waits until the other

master completes its transaction When the bus is granted

the device reads the descriptor from system memory and

loads the address pointer and byte count It then begins to

read data from system memory and buffers it in the posted

write buffers until the buffer is full When the buffer is full

the device releases the PCI bus When the device sees data

in the buffer it begins to write to the drive The device will

request the PCI bus whenever the posted write buffer is

either empty or half full If the posted write buffer is empty

(initial condition or due to another master on the PCI bus

interrupting the transfer) then the device reads in 4 Dwords

from memory filling the buffers If the posted write buffer is

half full then the device reads in 2 Dwords from memory

filling the buffers If another master gets ownership of the

bus after it released the bus the device continues to write

data to the drive emptying the write buffers The device con-

tinues to request the PCI bus if the byte count is not 0 and

EOT e 0 and the buffer is empty When it receives a grant

the device bursts in data (4Dwords) into the write buffer until

it is full When the byte count is 0 and it was the last descrip-

tor (EOT is 1) the device relinquishes the bus while the write

buffers are being emptied out onto the IDE bus If it wasn’t

the last descriptor (EOT is 0) the device reads the new

descriptor from memory while the device is writing out to the

drive the contents of the write buffers

Figure 10 shows the

DMA flow

TLF12497 – 35

FIGURE 10 Bus Master ReadsScenario 3

7424 PCI Bus Request

74241 PCI Master Reads

When the device wants to transfer data from memory to the

drive it will request the PCI bus under the following condi-

tions

(write FIFO empty or half full) and ((EOT is 0) or (byte count

is not 0))

The device will request the PCI bus when the write FIFO is

empty or half full and the DMA is active (not EOT or byte

count is not 0) When the device is granted the bus it will

assert FRAME

and read either 2 Dwords (if the FIFO was

half full) or 4 Dwords (if the FIFO was empty) from memory

and place it into the write FIFO As soon as 1 Dword is

placed into the FIFO the FIFO will no longer be empty so

therefore the PCI request will be deasserted until the data

from the FIFO are all written out onto the disk The device

will keep asserting FRAME

until all 2 or 4 Dwords are read

from memory If the device encounters a retry (STOP

as-

serted) while reading the 2 or 4 Dwords it will release

FRAME

and wait until the FIFO is half full or empty again

When the FIFO is half full the device will request the PCI

bus and will try to read 2 more Dwords from memory When

the FIFO is empty the device will request the PCI bus and

will try to read 4 more Dwords from memory

Each Dword read cycle is first qualified with the DMA being

active If the DMA goes inactive (EOT is 1 and byte count is

0) during any one of the 2 or 4 Dword reads from memory

the device will stop the reads and deassert FRAME

The

condition for deasserting FRAME

is expressed by the fol-

lowing

(burst in 2 or 4 Dwords) or ((EOT is 1) and (byte count 0))

If the byte count is programmed to be larger than the drive

transfer length the device will continue to read data from

memory and posting it into the write FIFO as long as the

FIFO is empty and the DMA is active When the FIFO is full

or the DMA goes inactive the device will release the PCI

bus Since the drive has completed the transfer it will gen-

erate an interrupt to the CPU even though some data is still

resident in the write FIFO When the CPU reads the status

registers of the device it will see the interrupt bit set and the

active bit either cleared or set The active bit will be cleared

if the device was able to write everything to the FIFO with

the last PCI request The active bit will be set if the device

was not able to write everything into the FIFO because the

FIFO was not emptied and therefore could not request the

PCI bus The contents of the write FIFO will be cleared

when the device sees a stop command and another start

command to that channel

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