AT89C51AC3-RDTIM datasheet(107/141 Pages) ATMEL

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107

AT89C51AC3

4383A–8051–10/04

ADC Converter

Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for re-

arming the interrupt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Table 57. Selected Analog input

Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range! (See section

“AC-DC”)

Clock Selection

The ADC clock is the same as CPU.

The typical maximum clock frequency for ADC is 700 KHz. A prescaler is featured

(ADCCLK) to generate the ADC clock from the oscillator frequency.

Figure 61. A/D Converter clock

ADC Standby Mode

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN

in ADCON register. In this mode its power dissipation is about 1 µW.

SCH2

SCH1

SCH0

Selected Analog input

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Prescaler ADCLK

A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

AT89C51AC3-RDTIM Datasheet(PDF) 107 Page - ATMEL Corporation

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