AT89C51AC3-RDTIM datasheet(108/141 Pages) ATMEL

108 / 141 page

108

AT89C51AC3

4383A–8051–10/04

IT ADC Management

An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

Figure 62. ADC Interrupt Structure

Routines examples

Configure P1.2 and P1.3 in ADC channels

// configure channel P1.2 and P1.3 for ADC

ADCF = 0Ch

// Enable the ADC

ADCON = 20h

Start a standard conversion

// The variable "channel" contains the channel to convert

// The variable "value_converted" is an unsigned int

// Clear the field SCH[2:0]

ADCON and = F8h

// Select channel

ADCON | = channel

// Start conversion in standard mode

ADCON | = 08h

// Wait flag End of conversion

while((ADCON and 01h)! = 01h)

// Clear the End of conversion flag

ADCON and = EFh

// read the value

value_converted = (ADDH << 2)+(ADDL)

Start a precision conversion (need interrupt ADC)

// The variable "channel" contains the channel to convert

// Enable ADC

EADC = 1

// clear the field SCH[2:0]

ADCON and = F8h

// Select the channel

ADCON | = channel

// Start conversion in precision mode

ADCON | = 48h

Note:

to enable the ADC interrupt:

EA = 1

ADEOC

ADCON.2

EADC

IEN1.1

ADCI

AT89C51AC3-RDTIM Datasheet(PDF) 108 Page - ATMEL Corporation

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