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WM9081 Datasheet(PDF) 13 Page - Cirrus Logic |
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WM9081 Datasheet(HTML) 13 Page - Cirrus Logic |
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13 / 103 page ![]() WM9081 Rev 4.0 13 AUDIO INTERFACE TIMING – MASTER MODE BCLK (output) LRCLK (output) DACDAT (input) tDL tDHT tDST Figure 2 Digital Audio Data Timing - Master Mode Test Conditions DCVDD=DBVDD=1.8V, AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, TA=+25 oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Timing Information LRCLK propagation delay from BCLK falling edge tDL 10 ns DACDAT setup time to BCLK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns |
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