WM9081 datasheet(21/103 Pages) CIRRUS

21 / 103 page

WM9081

Rev 4.0

The WM9081 supports the following read and write operations:



Single write



Single read



Multiple write using auto-increment



Multiple read using auto-increment

The sequence of signals associated with a single register write operation is illustrated in Figure 11.

SDIN

SCLK

device address

data bits B15 – B8

B15

Note: The SDIN pin is used as input for the control register address and data; SDIN is

pulled low by the receiving device to provide the acknowledge (ACK) response

R/W

data bits B7 – B0

START

Write

ACK

STOP

ACK

Figure 11 Control Interface 2-wire Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 12.

SDIN

SCLK

device address

Note: The SDIN pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses

R/W

B15

data bits B15 – B8

START

Write

ACK

R/W

Read

data bits B15 – B8

ACK

STOP

ACK

Rpt

START

Figure 12 Control Interface 2-wire Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 4.

Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.

This feature is enabled by default; it is described in Table 5 below.

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge

Stop Condition

R/ W

¯¯

0 = Write

1 = Read

[White field]

Data flow from bus master to WM9081

[Grey field]

Data flow from WM9081 to bus master

Table 4 Control Interface Terminology

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