PALCE29MA16 datasheet(2/25 Pages) AMD

2 / 25 page

AMD

2-350

PALCE29MA16H-25

GENERAL DESCRIPTION (continued)

semicustom solutions such as gate arrays and standard

cells, including reduced development time and low up-

front development cost.

The PALCE29MA16 uses the familiar sum-of-products

(AND-OR) structure, allowing users to customize logic

functions by programming the device for specific appli-

cations. It provides up to 29 array inputs and 16 outputs.

It incorporates AMD’s unique input/output logic macro-

cell which provides flexible input/output structure and

polarity, flexible feedback selection, multiple Output En-

able choices, and a programmable clocking scheme.

The macrocells can be individually programmed as

combinatorial, registered, or latched with active-HIGH

or active-LOW polarity. The flexibility of the logic macro-

cells permits the system designer to tailor the device to

particular application requirements.

Increased logic power has been built into the

PALCE29MA16 by providing a varied number of logic

product terms per output. Of the 16 outputs, 8 outputs

have 4 product terms each, 4 outputs have 8 product

terms each, and the other 4 outputs have 12 product

terms each. This varied product-term distribution allows

complex functions to be implemented in a single PAL

device. Each output can be dynamically controlled by a

common Output Enable pin or Output Enable product

term. Each output can also be permanently enabled or

disabled.

System operation has been enhanced by the addition of

common asynchronous-Preset and Reset product

terms

and

power-up

Reset

feature.

The

PALCE29MA16 also incorporates Preload and Obser-

vability functions which permit full logic verification of

the design.

The PALCE29MA16 is offered in the space-saving

300-mil SKINNYDIP package as well as the plastic

leaded chip carrier package.

CONNECTION DIAGRAMS

Top View

I/OF7

SKINNYDIP

CLK/

I/OF3

VCC

I/O7

I/O5

GND

I/OF2

I/O1

I/OF1

I/OF6

I/O6

I/OF0

I/O0

I/O3

I/O2

I/O4

I/OF5

I/OF4

PLCC

Note:

Pin 1 is marked for orientation.

428 27 26

I/O7

I/O6

I/O5

I/O4

I/OF5

I/O0

I/O2

I/O3

I/OF2

I/OF6

I/OF1

12 13

15 16

I/O1

PIN DESIGNATIONS

CLK/

= Clock or Latch Enable

GND

= Ground

= Input

I/O

= Input/Output

I/OF

= Input/Output with Dual Feedback

VCC

= Supply Voltage

= No Connection

08811G-2

08811G-3

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