PALCE29MA16 datasheet(4/25 Pages) AMD

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AMD

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PALCE29MA16H-25

FUNCTIONAL DESCRIPTION

Inputs

The PALCE29MA16 has 29 inputs to drive each product

term (up to 58 inputs with both TRUE and complement

versions available to the AND array) as shown in the

block diagram in Figure 1. Of these 29 inputs, 4 are

dedicated inputs, 16 are from eight I/O logic macrocells

with two feedbacks, 8 are from other I/O logic macro-

cells with single feedback and one is the I/

OE input.

Initially the AND-array gates are disconnected from all

the inputs. This condition represents a logical TRUE for

the AND array. By selectively programming the EE cells,

the AND array may be connected to either the TRUE in-

put or the complement input. When both the TRUE and

complement inputs are connected, a logical FALSE re-

sults at the output of the AND gate.

Product Terms

The degree of programmability and complexity of a PAL

device is determined by the number of connections that

form the programmable-AND and OR gates. Each pro-

grammable-AND gate is called a product term. The

PALCE29MA16 has 178 product terms; 112 of these

product terms provide logic capability and others are ar-

chitectural product terms. Among the control product

terms, one is for Observability, and one is for Preload.

The Output Enable of each macrocell can be pro-

grammed to be controlled by a common Output Enable

pin or an individual product term. It may also be perma-

nently disabled. In addition, independent product terms

for each macrocell control Preset, Reset and CLK/

LE.

Each product term on the PALCE29MA16 consists of a

58-input AND gate. The outputs of these AND gates are

connected to a fixed-OR plane. Product terms are allo-

cated to OR gates in a varied distribution across the

device ranging from 4 to 12 wide, with an average of 7

logic product terms per output. An increased number of

product terms per output allows more complex functions

to be implemented in a single PAL device. This flexibility

aids in implementing functions such as counters, exclu-

sive-OR functions, or complex state machines, where

different states require different numbers of product

terms.

Individual asynchronous-Preset and Reset product

terms are connected to all Registered or Latched I/Os.

When the asynchronous-Preset product term is as-

serted (HIGH) the register or latch will immediately be

loaded with a HIGH, independent of the clock. When the

asynchronous-Reset product term is asserted (HIGH)

the register or latch will be immediately loaded with a

LOW, independent of the clock. The actual output state

will depend on the macrocell polarity selection. The

latches must be in latched mode (not transparent mode)

for the Reset, Preset, Preload, and power-up Reset

modes to be meaningful.

Input/Output Logic Macrocells

The I/O logic macrocell allows the user the flexibility of

defining the architecture of each input or output on an in-

dividual basis. It also provides the capability of using the

associated pin either as an input or an output.

The PALCE29MA16 has 16 macrocells, one for each

I/O pin. Each I/O macrocell can be programmed for

combinatorial, registered or latched operation (see Fig-

ure 2). Combinatorial output is desired when the PAL

device is used to replace combinatorial glue logic. Reg-

isters and Latches are used in synchronous logic

applications. Registers and Latches with product term

controlled clocks can also be used in asychronous

application.

Preset

Reset

1 1

1 0

0 1

0 0

Common I/

OE (Pin)

Individual OE

Individual Asynchronous Preset

P7 or P11

Common CLK/

LE (PIN)

Individual CLK/

Individual Asynchronous Reset

To AND Array

I/O

VCC

0 1

1 1

1 0

0 0

1 1

0 1

1 0

0 0

CLK/

08811G-4

Figure 2a. PALCE29MA16 Macrocell (Single Feedback)

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