PALCE29MA16 datasheet(5/25 Pages) AMD

5 / 25 page

AMD

2-353

PALCE29MA16H-25

The output polarity for each macrocell in each of the

three modes of operation is user-selectable, allowing

complete flexibility of the macrocell configuration.

Eight of the macrocells (I/OF0–I/OF7) have two inde-

pendent feedback paths to the AND array (see Figure

2b). The first is a dedicated I/O pin feedback to the AND

array for combinatorial input. The second path consists

of a direct register/latch feedback to the array. If the pin

is used as a dedicated input using the first feedback

path, the register/latch feedback path is still available to

the AND array. This path provides the capability of using

the register/latch as a buried state register/latch. The

other eight macrocells have a single feedback path to

the AND array. This feedback is user-selectable as

either an I/O pin or a register/latch feedback (see

Figure 2a).

Each macrocell can provide true input/output capability.

The user can select each macrocell register/latch to be

driven by either the signal generated by the AND-OR ar-

ray or the corresponding I/O pin. When the I/O pin is se-

lected as the input, the feedback path provides the

each macrocell is also user-programmable for regis-

tered, latched, or combinatorial input.

The PALCE29MA16 has a dedicated CLK/

LE pin and

one individual CLK/

LE product term or macrocell. All

macrocells have a programmable switch to choose be-

tween the CLK/

LE pin and the CLK/LE product term as

the clock or latch enable signal. These signals are clock

signals for macrocells configured as registers and latch

enable signals for macrocells configured as latches.

The polarity of these CLK/

LE signals is also individually

programmable. Thus different registers or latches can

be driven by different clocks and clock phases.

The Output-Enable mode of each of the macrocells can

be selected by the user. The I/O pin can be configured

as an output pin (permanently enabled) or as an input

pin (permanently disabled). It can also be configured as

a dynamic I/O controlled by the Output Enable pin or by

a product term.

I/O Logic Macrocell Configuration

AMD’s unique I/O macrocell offers major benefits

through its versatile, programmable input/output cell

structure, multiple clock choices, flexible Output Enable

and feedback selection. Eight I/O macrocells with single

feedback contain 9 EE cells, while the other eight ma-

crocells contain 8 EE cells for programming the input/

output functions (see Table 1).

EE cell S1 controls whether the macrocell will be combi-

natorial or registered/latched. S0 controls the output po-

larity (active-HIGH or active-LOW). S2 determines

whether the storage element is a register or a latch. S3

allows the use of the macrocell as an input register/latch

or as an output register/latch. It selects the direction of

the data path through the register/latch. If connected to

the usual AND-OR array output, the register/latch is an

output connected to the I/O pin. If connected to the I/O

pin, the register/latch becomes an input register/latch to

the AND array using the feedback data path.

Programmable EE cells S4 and S5 allow the user to se-

lect one of the four CLK/

LE signals for each macrocell.

S6 and S7 are used to control Output Enable as pin con-

trolled, product-term controlled, permanently enabled or

permanently disabled. S8 controls a feedback multi-

plexer for the macrocells with a single feedback path

only.

Using the programmable EE cells S0–S8 various input

and output configurations can be selected. Some of the

possible configuration options are shown in Figure 3.

In the erased state (charged, disconnected), an archi-

tectural cell is said to have a value of “1”; in the pro-

grammed state (discharged, connected to GND), an

architectural cell is said to have a value of “0.”

Preset

Reset

1 1

1 0

0 1

0 0

Common I/

OE (Pin)

Individual OE

Individual Asynchronous Preset

Common CLK/

LE (PIN)

Individual CLK/

Individual Asynchronous Reset

To AND Array

I/OF

VCC

0 1

1 1

1 0

0 0

1 1

0 1

1 0

0 0

CLK/

RFX

To AND Array

Figure 2b. PALCE29MA16 Macrocell (Dual Feedback)

08811G-5

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