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AR0130CSSC00SPBA0-DP1 Datasheet(PDF) 12 Page - ON Semiconductor

Part # AR0130CSSC00SPBA0-DP1
Description  1/3?릋nch CMOS Digital Image Sensor
PDF  39 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

AR0130CSSC00SPBA0-DP1 Datasheet(HTML) 12 Page - ON Semiconductor

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Table 4. FRAME TIME (Example Based on 1280 x 960, 45 Frames Per Second)
Parameter
Timing at 74.25 MHz
Equation
Name
Nrows x (tROW)
Frame valid time
Context A: ((R0x3006−R0x3002+1)*(A+Q))−Q+P1+P2
Context B: ((R0x3090−R0x308C+1)*(A+Q))−Q+P1+P2
1,583,642 pixel clocks
= 21.33 ms
F
Total frame time
V + (Nrows x (A + Q))
1,633,500 pixel clocks
= 22.22 ms
Sensor timing is shown in terms of pixel clock cycles (see
Figure 8). The recommended pixel clock frequency is
74.25 MHz. The vertical blanking and the total frame time
equations assume that the integration time (coarse
integration time plus fine integration time) is less than the
number of active lines plus the blanking lines:
WindowHeight ) VerticalBlanking
(eq. 1)
If this is not the case, the number of integration lines must
be used instead to determine the frame time, (see Table 5).
In this example, it is assumed that the coarse integration time
control is programmed with 2000 rows and the fine shutter
width total is zero.
For Master mode, if the integration time registers exceed
the total readout time, then the vertical blanking time is
internally extended automatically to adjust for the additional
integration time required. This extended value is not written
back
to
the
frame_length_lines
register.
The
frame_length_lines register can be used to adjust
frame−to−frame readout time. This register does not affect
the exposure time but it may extend the readout time.
Table 5. FRAME TIME: LONG INTEGRATION TIME
Parameter
Name
Equation
Timing at 74.25 MHz
F’
Total frame time (long
integration time)
Context A: (R0x3012 x (A + Q)) + R0x3014 + P1 + P2
Context B: (R0x3016 x (A + Q)) + V R0x3018 + P1 + P2
3,300,012 pixel clocks
= 44.44 ms
NOTE: The AR0130 uses column parallel analog−digital converters; thus short line timing is not possible. The minimum total line time is
1390 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 110.
Exposure
Total
integration
time
is
the
result
of
Coarse_Integration_Time
and
Fine_Integration_Time
registers, and depends also on whether manual or automatic
exposure is selected.
The actual total integration time, tINT is defined as:
tINT + tINTCoarse * 410 * tINTFine
(eq. 1)
= (number of lines of integration x line time) − (410 pixel
clocks of conversion time overhead) − (number of pixels of
integration x pixel time)
where:
• Number of Lines of Integration (Auto Exposure
Control: Enabled)
When automatic exposure control (AEC) is enabled, the
number of lines of integration may vary from frame to
frame, with the limits controlled by R0x311E
(minimum auto exposure time) and R0x311C
(maximum auto exposure time).
• Number of Lines of Integration (Auto Exposure
Control: Disabled)
If AEC is disabled, the number of lines of integration
equals the value in R0x3012 (context A) or R0x3016
(context B).
• Number of Pixels of Integration
The number of fine shutter width pixels is independent
of AEC mode (enabled or disabled):
♦ Context A: the number of pixels of integration
equals the value in R0x3014.
♦ Context B: the number of pixels of integration
equals the value in R0x3018.
Typically, the value of the Coarse_Integration_Time
register is limited to the number of lines per frame (which
includes vertical blanking lines), such that the frame rate is
not affected by the integration time. For more information
on coarse and fine integration time settings limits, please
refer to the Register Reference document.



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