AR0130CSSC00SPBA0-DP1 datasheet(27/39 Pages) ONSEMI

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AR0130CS

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ELECTRICAL SPECIFICATIONS

Unless otherwise stated, the following specifications

apply to the following conditions:

VDD = 1.8 V –0.10/+0.15;

VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V ±0.3 V;

VDD_SLVS = 0.4 V –0.1/+0.2;

TA = −30°C to +70°C;

Output Load = 10 pF;

Frequency = 74.25 MHz.

Two-Wire Serial Register Interface

The electrical characteristics of the two-wire serial

Table 8.

Figure 28. Two-Wire Serial Bus Timing Parameters

SDATA

SCLK

tSU;DAT

tHD;STA

tSU;STO

tSU;STA

tBUF

tHD;DAT

tHIGH

tLOW

tHD;STA

NOTE: Read sequence: For an 8-bit READ, read waveforms start after READ command and register address are issued.

Table 8. TWO-WIRE SERIAL BUS CHARACTERISTICS

(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25°C)

Parameter

Symbol

Standard Mode

Fast-Mode

Unit

Min

Max

Min

Max

SCLK Clock Frequency

fSCL

100

400

kHz

After This Period, the First Clock

Pulse is Generated

tHD;STA

4.0

−

0.6

−

LOW Period of the SCLK Clock

tLOW

4.7

−

1.3

−

HIGH Period of the SCLK Clock

tHIGH

4.0

−

0.6

−

Set-up Time for a Repeated

START Condition

tSU;STA

4.7

−

0.6

−

Data Hold Time

tHD;DAT

0 (Note 4)

3.45 (Note 5)

0 (Note 6)

0.9 (Note 5)

Data Set-up Time

tSU;DAT

250

−

100 (Note 6)

−

Rise Time of both SDATA and

SCLK Signals

−

1000

20 + 0.1Cb

(Note 7)

300

Fall Time of both SDATA and SCLK

Signals

−

300

20 + 0.1Cb

(Note 7)

300

Set-up Time for STOP Condition

tSU;STO

4.0

−

0.6

−

1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I2C-compatible.

3. All values referred to VIHmin = 0.9 VDD_IO and VILmax = 0.1 VDD_IO levels. Sensor EXTCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of

SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This

will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW

period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Stan-

dard-mode I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

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