AR0130CS

www.onsemi.com

4

Figure 2. Typical Configuration: Parallel Pixel Data Interface

From Controller

Master Clock

(6 − 50 MHz)

Digital

I/O

Digital

Core

PLL

Analog

TRIGGER

OE_BAR

STANDBY

RESET_BAR

Reserved

PIXCLK

FRAME_VALID

LINE_VALID

Analog

Digital

Ground

Analog

Ground

EXTCLK

To Controller

Notes:

1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.

4. ON Semiconductor recommends that VDD_SLVS pad (only available in bare die) is left unconnected.

5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as

close as possible to the pad. Actual values and results may vary depending on layout and design considerations.

Check the AR0130 demo headboard schematics for circuit recommendations.

6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital

power planes is minimized.

Table 3. PAD DESCRIPTIONS

Name

Type

Description

STANDBY

Input

Standby−mode enable pin (active HIGH).

Power

PLL power.

Power

Analog power.

EXTCLK

Input

External input clock.

Power

Digital power (do not connect).

Power

Digital ground.

Power

Digital power.

Power

Analog ground.

Input

Two−Wire Serial Interface address select.

Input

Two−Wire Serial Interface clock input.

I/O

Two−Wire Serial Interface data I/O.