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AR0130CSSC00SPBA0-DP1 Datasheet(PDF) 29 Page - ON Semiconductor |
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AR0130CSSC00SPBA0-DP1 Datasheet(HTML) 29 Page - ON Semiconductor |
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29 / 39 page  AR0130CS www.onsemi.com 29 Table 9. I/O TIMING CHARACTERISTICS (2.8 V VDD_IO) (Note 8) Conditions: fPIXCLK = 74.25 MHz (720 P 60 fps) VDD_IO = 2.8 V; Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports Symbol Unit Max Typ Min Condition Definition Input Clock Duty Cycle 45 50 55 % tJITTER (Note 9) Input Clock Jitter at 27 MHz − 600 − ps tcp EXTCLK to PIXCLK Propagation Delay Nominal Voltages, PLL Disabled, PIXCLK Slew Rate = 4 12 − 20 ns fPIXCLK PIXCLK Frequency (Note 9) 6 − 74.25 MHz tRP PIXCLK Rise Time Slew Rate Setting = 4 1.60 2.70 7.50 ns tFP PIXCLK Fall Time Slew Rate Setting = 4 1.50 2.60 7.20 ns PIXCLK Duty Cycle 45 50 55 % tPIXJITTER Jitter on PIXCLK − 1 − ns tPD PIXCLK to Data[11:0] PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −2.5 − 3.5 ns tPFH PIXCLK to FV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −2.5 − 0.5 ns tPLH PIXCLK to LV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −3.0 − 0.0 ns tPFL PIXCLK to FV LOW PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −2.5 − 0.5 ns tPLL PIXCLK to LV LOW PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −3.0 − 0.0 ns CLOAD Output Load Capacitance − 10 − pF CIN Input Pin Capacitance − 2.5 − pF 8. Minimum and maximum values are for the spec limits: 3.1 V, −30°C and 2.50 V, 70°C. All values are taken at the 50% transition point. 9. Jitter from PIXCLK is already taken into account as the data of all the output parameters. Table 10. I/O TIMING CHARACTERISTICS (1.8 V VDD_IO) (Note 10) Conditions: fPIXCLK = 74.25 MHz (720 P 60 fps) VDD_IO = 1.8 V; Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports Symbol Definition Condition Min Typ Max Unit fEXTCLK Input Clock Frequency PLL Enabled 6 − 50 MHz tEXTCLK Input Clock Period PLL Enabled 20 − 166 ns tR Input Clock Rise Time − 3 − ns tF Input Clock Fall Time − 3 − ns Input Clock Duty Cycle 45 50 55 % tJITTER (Note 11) Input Clock Jitter at 27 MHz − 600 − ps tcp EXTCLK to PIXCLK Propagation Delay Nominal Voltages, PLL Disabled, Slew Setting = 4 12 − 20 ns fPIXCLK PIXCLK Frequency (Note 11) 6 74.25 MHz tRP Pixel Rise Time Slew Rate Setting = 4 2.50 4.30 7.10 ns tFP Pixel Fall Time Slew Rate Setting = 4 2.20 3.80 6.50 ns PIXCLK Duty Cycle PLL Enabled 45 50 55 % tPIXJITTER Jitter on PIXCLK − 1 − ns tPD PIXCLK to Data Valid PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.5 − 2.0 ns tPFH PIXCLK to FV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.0 − −0.5 ns tPLH PIXCLK to LV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.0 − −0.5 ns 10.Minimum and maximum values are are for the spec limits: 1.95 V, −30°C and 1.70 V, 70°C. All values are taken at the 50% transition point. 11. Jitter from PIXCLK is already taken into account as the data of all the output parameters. |
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