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CY8C52LP Datasheet(PDF) 94 Page - Cypress Semiconductor

Part # CY8C52LP
Description  Programmable System-on-Chip (PSoC짰)
PDF  114 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C52LP Datasheet(HTML) 94 Page - Cypress Semiconductor

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PSoC® 5LP: CY8C52LP Family
Datasheet
Document Number: 001-84933 Rev. *L
Page 94 of 114
11.7.3 Nonvolatile Latches (NVL)
11.7.4 SRAM
Table 11-46. NVL DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Erase and program voltage
VDDD pin
1.71
–
5.5
V
Table 11-47. NVL AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
NVL endurance
Programmed at 25 °C
1K
–
–
program/
erase
cycles
Programmed at 0 °C to 70 °C
100
–
–
program/
erase
cycles
NVL data retention time
Average ambient temp. TA ≤ 55 °C
20
–
–
years
Average ambient temp. TA ≤ 85 °C
10
–
–
years
Note
62. Based on device characterization (Not production tested).
Table 11-48. SRAM DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
VSRAM
SRAM retention voltage[62]
1.2
–
–
V
Table 11-49. SRAM AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FSRAM
SRAM operating frequency
DC
–
80.01
MHz



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