Document Number: 001-44060 Rev. *O

Page 5 of 31

CY7C1663KV18/CY7C1665KV18

Pin Definitions

Pin Name

I/O

Pin Description

Input-

Synchronous

Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.

CY7C1663KV18

CY7C1665KV18

WPS

Input-

Synchronous

Write port select

 Active Low. Sampled on the rising edge of the K clock. When asserted active, a

Input-

Synchronous

Byte write select 0, 1, 2, and 3

 Active Low. Sampled on the rising edge of the K and K clocks when

write operations are active. Used to select which byte is written into the device during the current portion

of the write operations. Bytes not written remain unaltered.

CY7C1663KV18

CY7C1665KV18

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A

Input-

Synchronous

Address inputs. Sampled on the rising edge of the K clock during active read and write operations.

These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 8M × 18 (4 arrays each of 2M × 18) for CY7C1663KV18 and 4M × 36 (4 arrays each of

1M × 36) for CY7C1665KV18. Therefore, only 21 address inputs are needed to access the entire memory

array of CY7C1663KV18 and 20 address inputs for CY7C1665KV18. These inputs are ignored when

the appropriate port is deselected.

Outputs-

Synchronous

Data output signals. These pins drive out the requested data when the read operation is active. Valid

data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the

CY7C1663KV18

CY7C1665KV18

RPS

Input-

Synchronous

Read port select

 Active Low. Sampled on the rising edge of positive input clock (K). When active, a

read operation is initiated. Deasserting deselects the read port. When deselected, the pending access

is allowed to complete and the output drivers are automatically tristated following the next rising edge of

the K clock. Each read access consists of a burst of four sequential transfers.

QVLD

Valid output

indicator

Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.

K

Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device

K

Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and

CQ

Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.

CQ

Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.

ZQ

Input

Output impedance matching input. This input is used to tune the device outputs to the system data

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

unconnected.

DOFF

Input

PLL turn off

 Active Low. Connecting this pin to ground turns off the PLL inside the device. The timings

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull-up through a 10 K

 or less pull-up resistor. The device behaves in QDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to

167 MHz with QDR I timing.

TDO

Output

Test data-out (TDO) pin for JTAG.

TCK

Input

Test clock (TCK) pin for JTAG.