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CY7C1663KV18 Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1663KV18
Description  144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
PDF  31 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1663KV18 Datasheet(HTML) 10 Page - Cypress Semiconductor

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Document Number: 001-44060 Rev. *O
Page 10 of 31
CY7C1663KV18/CY7C1665KV18
Write Cycle Descriptions
The write cycle description table for CY7C1663KV18 follows. [11, 12]
BWS0 BWS1
K
K
Comments
L
L
L–H
–
During the data portion of a write sequence
CY7C1663KV18
both bytes (D[17:0]) are written into the device.
L
L
–
L–H During the data portion of a write sequence:
CY7C1663KV18
both bytes (D[17:0]) are written into the device.
L
H
L–H
–
During the data portion of a write sequence:
CY7C1663KV18
only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
–
L–H During the data portion of a write sequence
CY7C1663KV18
only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
–
During the data portion of a write sequence
CY7C1663KV18
only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
–
L–H During the data portion of a write sequence
CY7C1663KV18
only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
L–H
–
No data is written into the devices during this portion of a write operation.
H
H
–
L–H No data is written into the devices during this portion of a write operation.
Notes
11. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
12. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a
write cycle, as long as the setup and hold requirements are achieved.



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