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IMX7SCEC Datasheet(PDF) 33 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 33 Page - NXP Semiconductors |
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33 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 33 Figure 4. i.MX 7Solo power-up sequence 4.1.9 Power-down sequence The i.MX7 processors have the following power-down sequence requirements: • VDD_SNVS _IN to be turned off last after any other power supply. • NVCC_DRAM/NVCC_DRAM_CKE to be turned off before VDD_SOC. • There are no special timing requirements forVDD_USB_OTG1_3P3_IN andVDD_USB_OTG2_3P3_IN. The power-down sequence is shown in Figure 5 with the following timing parameters: T4 Time from first power rails (except SNVS) to ramp down to all the power rails (except SNVS) get to ground, minimal delay is 0ms, no max delay requirement. T5 Time from all the power rails power down (except SNVS) to SVNS power down, minimal delay is 0ms, no max delay requirement. T7 Time from NVCC_DRAM/NVCC_DRAM_CKE power down to VDD_SOC power down, minimal delay is 0ms, no max delay requirement. |
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