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M29DW128F Datasheet(PDF) 43 Page - STMicroelectronics |
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M29DW128F Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 93 page  M29DW128F 6 Command Interface 43/93 Set Non- Volatile Modify Protection Bit(5) (6) 6 555 AA 2AA 55 555 60 (BA)/ NVMP 68 (BA)/ NVMP 48 (BA)/ NVMP DQ0 Verify Non- Volatile Modify Protection Bit 4 555 AA 2AA 55 555 60 (BA)/ NVMP 48 (BA)/ NVMP DQ0 Clear Non- Volatile Modify Protection Bits(12)(13)(14) 6 555 AA 2AA 55 555 60 NVMP 60 (BA)/ NVMP 40 (BA)/ NVMP DQ0 Set Lock-Down bit 3 555 AA 2AA 55 555 78 Verify Lock- Down bit(15) 4 555 AA 2AA 55 555 58 BA DQ1 Set Lock Bit(7) 4 555 AA 2AA 55 555 48 BA X1h Clear Lock Bit(7) 4 555 AA 2AA 55 555 48 BA X0h Verify Lock Bit 4 555 AA 2AA 55 555 58 BA DQ0 Set Standard Protection Mode(5)(6) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL DQ0 Verify Standard Protection Mode(5) 4 555 AA 2AA 55 555 60 SL DQ0 1. Grey cells represent Read cycles. The other cells are Write cycles. 2. SA Protection Group Address, BA Any address in the Block, BKA Bank Address, SL Standard Protection Mode Lock bit Address, PL Password Protection Mode Lock Bit Address, PW Password Data, PWA Password Address, RPW Password Data Being Verified, NVMP Non-Volatile Modify Protection Bit Address, OW Extended Block Protection Bit Address, X Don’t Care. All values in the table are in hexadecimal. 3. Addresses are described in Table 17: Protection Command Addresses. 4. During Unlock and Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are Don't Care. 5. A Reset Command must be issued to return to the Read mode. 6. The 4th Bus Write cycle programs a protection bit (Extended Block Protection bit, Password Protection Mode Lock bit, Standard Protection Mode Lock bit, and a block NVMP bit). The 5th and 6th cycles verify that the bit has been successively programmed when DQ0=1. If DQ0=0 in the 6th cycle, the program command must be issued again and verified again. A 100µs delay is required between the 4th and the 5th cycle. 7. Data is latched on the rising edge of W. 8. The entire command sequence must be entered for each portion of the password. 9. The command sequence returns FFh if the Password Protection Mode locking bit is set. 10. The password is written over four consecutive cycles, at addresses [0-3] 11. A 2µs timeout is required between any two portions of the password. 12. A 10ms delay is required between the 4th and the 5th cycle. 13. A 12ms timeout is required between cycles 4 and 5. Command Bus Operations(1)(2)(3)(4) 1st 2nd 3rd 4th 5th 6th 7th Add Data Add Data Add Data Add Data Add Data Add Data Add Data |
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