M29DW128F datasheet(46/93 Pages) STMICROELECTRONICS

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7 Status Register

M29DW128F

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7.3

Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error

Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct

data to the memory. If the Error Bit is set a Read/Reset command must be issued before other

commands are issued. The Error bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do

so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of

the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’

to ’1’.

7.4

Erase Timer Bit (DQ3)

The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation

during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase

Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’

and additional blocks to be erased may be written to the Command Interface. The Erase Timer

Bit is output on DQ3 when the Status Register is read.

7.5

Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase

operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc.,

with successive Bus Read operations from addresses within the blocks being erased. A

protected block is treated the same as a block not being erased. Once the operation completes

the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read operations from addresses within the blocks being erased. Bus Read

operations to addresses within blocks not being erased will output the memory array data as if

in Read mode.

After an Erase operation that causes the Error Bit to be set, the Alternative Toggle Bit can be

used to identify which block or blocks have caused the error. The Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within

blocks that have not erased correctly. The Alternative Toggle Bit does not change if the

addressed block has erased correctly.

Figure 16 and Figure 17 describe Alternative Toggle Bit timing waveform.

7.6

Write to Buffer and Program Abort Bit (DQ1)

The Write to Buffer and Program Abort bit, DQ1, is set to ‘1’ when a Write to Buffer and

Program operation aborts. The Write to Buffer and Program Abort and Reset command must

be issued to return the device to Read mode (see Write to Buffer and Program in COMMANDS

section).

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