TLE9461ESV33 datasheet(92/140 Pages) INFINEON

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TLE9461ES V33

Lite CAN SBC Family

Supervision Functions

Datasheet

Rev.1.1

2019-09-27

12.8

Thermal Protection

Three independent and different thermal protection features are implemented in the SBC according to the

system impact:

• Individual thermal shutdown of specific blocks

• Temperature prewarning of main microcontroller supply VCC1

• SBC thermal shutdown due to VCC1 overtemperature

12.8.1

Individual Thermal Shutdown

As a first-level protection measure the output stages VCC2 and CAN are independently switched Off if the

respective block reaches the temperature threshold TjTSD1_1 / TjTSD1_2. Then the TSD1 bit is set. This bit can only

be cleared via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the

thermal shutdown protection is only active if the respective block is On.

The respective modules behave as follows:

• VCC2: Is switched to Off and the control bits VCC2_ON are cleared. The status bit VCC2_OT is set. Once the

overtemperature condition is not present anymore, then VCC2 has to be configured again by SPI.

• CAN: The transmitter is disabled and stays in CAN Normal Mode acting like CAN Receive only mode. The

status bits CAN_FAIL = ‘01’ are set. Once the overtemperature condition is not present anymore, then the

CAN transmitter is automatically switched On.

Note:

The diagnosis bits are not cleared automatically and have to be cleared via SPI once the

overtemperature condition is not present anymore.

12.8.2

Temperature Prewarning

As a next level of thermal protection a temperature prewarning is implemented. If the main supply VCC1

exceeds the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only

be cleared via SPI once the overtemperature is not present anymore.

12.8.3

SBC Thermal Shutdown

As the highest level of thermal protection a temperature shutdown of the SBC is implemented if the main

supply VCC1 reaches the thermal shutdown temperature threshold TjTSD1_1 / TjTSD1_2. Once a TSD2 event is

detected SBC Fail-Safe Mode is entered. Only when device temperature falls below the TSD2 threshold then

the device remains in SBC Fail-Safe Mode for tTSD2 to allow the device to cool down. After this time has expired,

the SBC automatically changes via SBC Restart Mode to SBC Normal Mode (see also Chapter 5.1.6).

When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in SBC

Normal Mode once the overtemperature is not present anymore.

For increased robustness it is possible to extend the TSD2 waiting time by 64x of tTSD2 after 16 consecutive

TSD2 events by setting the SPI bit TSD2_DEL. The counter is incremented with each TSD2 event even if the bit

TSD2 is not cleared. Once the counter has reached the value 16, then the bit TSD2_SAFE is set and the

extended TSD2 waiting time is active. The extended waiting time is kept until TSD2_SAFE is cleared. The TSD

counter is cleared when TSD2 or TSD2_DEL is cleared.

Note:

In case a TSD2 overtemperature occurs while entering SBC Sleep Mode then SBC Fail-Safe mode is

entered.

Note:

To enable higher ambient temperatures the thermal shutdown thresholds can be increased by 10K

for TSD1 and TSD2 by setting the bit TSD_THR.

TLE9461ESV33 Datasheet(PDF) 92 Page - Infineon Technologies AG

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