H8SLASH3002 datasheet(112/700 Pages) RENESAS

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5.4.3 Interrupt Response Time

Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until

the first instruction of the interrupt service routine is executed.

Table 5-5 Interrupt Response Time

External Memory

8-Bit Bus

16-Bit Bus

No. Item

2 States

3 States

2 States

3 States

Interrupt priority decision

2*1

Maximum number of states

1 to 23

1 to 27

1 to 31*4

1 to 23

1 to 25*4

until end of current instruction

Saving PC and CCR to stack

12*4

46*4

Vector fetch

12*4

46*4

Instruction prefetch*2

4812*4

46*4

Internal processing*3

44444

Total

19 to 41

31 to 57

43 to 73

19 to 41

25 to 49

Notes: 1. 1 state for internal interrupts.

2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt

service routine.

3. Internal processing after the interrupt is accepted and internal processing after prefetch.

4. The number of states increases if wait states are inserted in external memory access.

On-Chip

Memory

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