H8SLASH3002 datasheet(114/700 Pages) RENESAS

114 / 700 page

5.5.2 Instructions that Inhibit Interrupts

The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs,

after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the

CPU is currently executing one of these interrupt-inhibiting instructions, however, when the

instruction is completed the CPU always continues by executing the next instruction.

5.5.3 Interrupts during EEPMOV Instruction Execution

The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.

When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the

transfer is completed, not even NMI.

When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are

not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at

a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.

Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:

L1:

EEPMOV.W

MOV.W R4,R4

BNE

5.5.4 Usage Notes

The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read

while set to 1. However, it is possible for the IRQnF flag to be cleared by mistake simply by

writing 0 to it, irrespective of whether it has been read while set to 1, with the result that interrupt

exception handling is not executed. This will occur when the following conditions are met.

1. Setting conditions

(1) Multiple external interrupts (IRQa, IRQb) are being used.

(2) Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and

clearing by hardware for the IRQbF flag.

(3) A bit-manipulation instruction is used on the IRQ status register for clearing the IRQaF flag,

or else ISR is read as a byte unit, the IRQaF flag bit is cleard, and the values read in the other

bits are written as a byte unit.

2. Generation conditions

(1) A read of the ISR register is executed to clear the IRQaF flag while it is set to1, then the

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