Datasheet

9

Rev. 1.10

2019-09-26

TLD2132-1EP

LITIX™ Basic+

General product characteristics

3.3

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 4

1) Not subject to production test, specified by design

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ.

Max.

Junction to Case

––

10

K/W

1)2)

P_4.3.1

Junction to Ambient 1s0p

board

–

–

61

56

–

–

K/W

1)3)

dissipation 1.5 W distributed statically and homogenously over all power stages

P_4.3.3

Junction to Ambient 2s2p

board

–

–

45

43

–

–

K/W

1)4)

(chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Total power

dissipation 1.5 W distributed statically and homogenously over all power stages

P_4.3.4