ZSSC3240CC1B datasheet(10/64 Pages) RENESAS

10 / 64 page

ZSSC3240

Datasheet

Nov.27.20

Page 10

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

ErrA,IC

ZSSC3240 accuracy

error

Accuracy error with an ideally linear

sensor (in temperature and measurand)

–

0.01

% FSO

Vioffsc

Correctable (in PGA),

absolute, differential input

offset

Programmable in 1mV steps; accuracy:

±5% referenced to nominal setup

-15

ADC,c

Correctable (in ADC),

relative, differential input

offset

Percentage of sensor signal offset

versus maximum sensor signal

–

Input

VINP, VINN

Absolute sensor input

Voltages at INP and INN pin; resulting

minimum/maximum differential voltages:

-700mV < VINdiff < 700mV

0.5

–

1.20

VTEXT

External temperature

diode or RTD input range

At TEXT pin

0.5

–

1.25

RSENSOR

External sensor (bridge)

resistance

VDDB = 1.75V

0.5

–

kΩ

For 4mA to 20mA current loop output

1.6

–

kΩ

|VDIFFin|

Differential input signal

range

Referenced to sensor supply (VDDAint);

leading to full scale analog excitation

2.6

700

Diagnostics

Ropen

Sensor connection loss;

i.e., open threshold

INP vs. INN

–

kΩ

Rshort

Sensor connection short

threshold

INP vs. INN; TEXT vs. VDDB

–

100

Ω

Vs,valid

Valid sensor input signal

Beyond Vs,valid, sensor connection checks

(such as in-range, etc.) signalize

Diagnostic FAULTs

0.44

–

1.31

Power-Up

tSTA1

Start-up Time

VDD ramp up to interface communication

–

tSTA2

VDD ramp up to analog operation

–

2.5

tWUP1

Wake-up Time

Sleep to Active State interface

communication

–

µs

tWUP2

Sleep to Active State analog operation

–

Oscillator

fCLK

Internal oscillator

frequency

5.9

6.0

6.1

MHz

Temperature Sensor(s)

rTemp

Internal temperature

sensor resolution

Setup: ADTTsens,int = 13-bit

–

Counts/K

Rt, Rt'

Internal low TC [f]

top/bottom resistance for

external temperature

Programmable with internal_rt and

extra_rt;

applied if temp_source

є {010; 110} (see

section 6.2.4)

1.34

–

kΩ

Interface and Memory

fC,SPI

SPI clock frequency

0.05

MHz

fC,I2C

I2C clock frequency

–

3.4

MHz

CDOWI

OWI data rate

0.33

–

kBit/s

tPROG

NVM program time

Programming time per 16-bit word

–

nNVM

NVM endurance

Number of reprogramming cycles

1000

10000

–

Numeric

tRET,NVM

Data retention

–

Years

[a]

Referenced to nominal value. Relative errors are typically < 1% for sensor bias current setups > 20µA.

[b]

PSRR = 20·log10(VDD/VDDB): will be improved when applying external filter elements at VDD and/or also using an external JFET

regulator.

[c]

This parameter must be taken into account if automatic common mode regulation in the PGA is switched off (pga_en_shift; see

section 6.2.1) and a non-symmetric sensor supply and input to the PGA ADC path have been configured.

[d]

There are several setups and parameters that allow optimizing and maximizing the output update rate; e.g., ADC and DAC

resolutions, configurations for the measurement sequence, usage of the internal or an external temperature sensor.

[e]

Vioffsc and ΔADC,c can be arbitrarily set up and combined. They work independently on each other.

[f]

Typical residual temperature variation of voltage across Rt, Rt': 10ppm/K; maximum deviation: 150ppm/K at

40kΩ and >100°C, all other setups and conditions < 60ppm/K.

[g]

ENOB = log2( 2

rADC / 3



Noise ) with, for example rADC[Bit] = 24.

ZSSC3240CC1B Datasheet(PDF) 10 Page - Renesas Technology Corp

ZSSC3240CC1B Datasheet(HTML) 10 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL