LTC7802EUFDM-3.3 datasheet(14/34 Pages) AD

14 / 34 page

LTC7802-3.3

Rev. 0

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OPERATION

Therefore, if Burst Mode is selected and the switching

frequency is synchronized to an external clock applied to

the PLLIN/SPREAD pin, the LTC7802-3.3 switches from

Burst Mode to forced continuous mode.

Frequency Selection, Spread Spectrum, and Phase-

Locked Loop (FREQ and PLLIN/SPREAD Pins)

The free running switching frequency of the LTC7802-

3.3 controllers is selected using the FREQ pin. Tying

FREQ to GND selects 350kHz while tying FREQ to INTVCC

selects 2.25MHz. Placing a resistor between FREQ and

GND allows the frequency to be programmed between

100kHz and 3MHz.

Switching regulators can be particularly troublesome for

applications where electromagnetic interference (EMI) is

a concern. To improve EMI, the LTC7802-3.3 can oper-

ate in spread spectrum mode, which is enabled by tying

the PLLIN/SPREAD pin to INTVCC. This feature varies the

switching frequency within typical boundaries of –12% to

+15% of the frequency set by the FREQ pin.

A phase-locked loop (PLL) is available on the LTC7802-

3.3 to synchronize the internal oscillator to an external

clock source connected to the PLLIN/SPREAD pin. The

LTC7802-3.3’s PLL aligns the turn-on of controller 1’s

external top MOSFET to the rising edge of the synchroniz-

ing signal. Thus, the turn-on of controller 2’s external top

MOSFET is 180° out-of-phase to the rising edge of the

external clock source.

The PLL frequency is prebiased to the free running fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL only needs to make slight changes in order to

synchronize the rising edge of the external clock to the

rising edge of TG1. For more rapid lock-in to the external

clock, use the FREQ pin to set the internal oscillator to

approximately the frequency of the external clock. The

LTC7802-3.3’s PLL is guaranteed to lock to an external

clock source whose frequency is between 100kHz and

3MHz.

The PLLIN/SPREAD pin is TTL compatible with thresholds

of 1.6V (rising) and 1.1V (falling) and is guaranteed to

operate with a clock signal swing of 0.5V to 2.2V.

Output Overvoltage Protection

Each channel has an overvoltage comparator that guards

against transient overshoots as well as other more serious

conditions that may overvoltage the output. When the

VOUT1, VFB2 pin rises more than 10% above its regula-

tion point, the top MOSFET is turned off and the bottom

MOSFET is turned on until the overvoltage condition is

cleared.

Foldback Current

When the output voltage falls to less than 50% of its

nominal level, foldback current limiting is activated, pro-

gressively lowering the peak current limit in proportion to

the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

interval (as long as the VFB voltage is keeping up with the

TRACK/SS1,2 voltage).

Power Good

Each channel has a PGOOD pin that is connected to an

open drain of an internal N-channel MOSFET. The MOSFET

turns on and pulls the PGOOD pin low when the VFB volt-

age is not within ±10% of the 0.8V reference. The PGOOD

pin is also pulled low when the RUN pin is low (shut

down). When the VFB voltage is within the ±10% require-

ment, the MOSFET is turned off and the pin is allowed to

be pulled up by an external resistor to a source no greater

than 6V, such as INTVCC.

LTC7802EUFDM-3.3 Datasheet(PDF) 14 Page - Analog Devices

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