AT25FF321A datasheet(48/119 Pages) DIALOG

48 / 119 page

Datasheet

2021-08-19

DS-AT25FF321A-181

Revision J

AT25FF321A

32-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory

with Multi-I/O Support

Commands and Addressing

A valid command or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host

controller must then clock out a valid 8-bit command on the SPI bus. Following the command, information such as address and

data bytes would then be clocked out by the host controller. All command, address, and data bytes are transferred with the most-

significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Commands not supported by the AT25FF321A are ignored by the device and no operation is started. The device continues to

ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). Also,

if the CS pin is deasserted before the complete command and address information are sent to the device, then no operation is

performed and the device simply returns to the idle state and waits for the next operation.

Depending on the command, up to three bytes of information may be required, representing address bits A23 - A0. Since the

upper address limit of the AT25FF321A memory array is 3FFFFFh, address bits A23 - A22 are always ignored by the device.

Table 17: Command Listing

Command Name

Section

in Doc.

Hex

Cmd

Transfer Type 1

Command

Address

Dummy

Data

Mode

Format

Bytes

Clocks

Bytes

Clocks

Bytes

Clocks

Bytes 2

Clocks

Read Commands

Read Array

6.1

03h

SPI

1-1-1

Var.

Var. x 8

Fast Read Array

6.1

0Bh

SPI

1-1-1

Var.

Var. x 8

Dual Output Read Array

6.2

3Bh

Dual

Output

1-1-2

Var.

Var. x 4

Quad Output Read Array

6.3

6Bh

Quad

Output

1-1-4

Var.

Var, x 2

XiP Mode Read Array (initial

transfer)

6.4

EBh

XiP

1-4-4

Var.

Var. x 2

Var.

Var. x 2

XiP Mode Read Array

(subsequent transfers)

6.4

---

XiP

0-4-4

Var.

Var. x 2

Var.

Var. x 2

XiP Mode Read Array - DWA

addr (initial transfer)

6.4

E7h

XiP

1-4-4

Var.

Var. x 2

Var.

Var. x 2

XiP Mode Read Array - DWA

addr, subsequent transfers

6.4

---

XiP

0-4-4

Var.

Var. x 2

Var.

Var. x 2

Program/Erase Commands

Block Erase (4 Kbytes)

6.5

20h

SPI

1-1-0

Block Erase (32 Kbytes)

6.5

52h

SPI

1-1-0

Block Erase (64 Kbytes)

6.5

D8h

SPI

1-1-0

Chip Erase

6.6

60h

SPI

1-0-0

6.6

C7h

SPI

1-0-0

Byte/Page Program

(1 - 256 bytes)

6.7

02h

SPI

1-1-1

Var.

(1 - 256)

Var. x 8

Sequential Program Mode 3

(first command)

6.8

ADh/

AFh

SPI

1-1-1

Sequential Program Mode

(subsequent commands)

6.8

ADh/

AFh

SPI

1-0-1

Dual Output Byte/Page

Program

6.9

A2h

Dual

Output

1-1-2

Var.

(1 - 256)

Var. x 4

AT25FF321A Datasheet(PDF) 48 Page - Dialog Semiconductor

AT25FF321A Datasheet(HTML) 48 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL