AT25FF321A datasheet(21/119 Pages) DIALOG

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Datasheet

2021-08-19

DS-AT25FF321A-181

Revision J

AT25FF321A

32-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory

with Multi-I/O Support

4.5 QUAD I/O OPERATION (1-4-4)

The AT25FF321A supports the Quad I/O mode which enhances overall throughput over the standard SPI and dual operation

modes by increasing the data transfer rate. In this mode, address and data are transferred on four pins; SI, SO, WP, and HOLD.

This means that only 1/4th the number of clocks are required to transfer the address and data relative to standard SPI mode. This

is known as a 1-4-4 transfer which is defined as: 1-pin command, 4-pin address, and 4-pin data (1-4-4)

In Quad I/O mode the command (C) is driven to the memory device on the SI (IO0) pin. During write operations, the SI (IO0), SO

(IO1), WP (IO2), and HOLD (IO3) pins switched to inputs and the address and data are driven on all four pins, allowing four bits

to be transferred on every clock. During read operations, once the command is transferred on the SI (IO0) pin, address is

transferred on the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins, allowing a 24-bit address to be transferred in only six clocks.

Once the address transfer is complete, these pins are switched to outputs and the data is driven on all four pins, allowing four

data bits to be transferred on every clock. Note that mode bits M[7:0] must not be in high-Z (tri-state) mode. For optimal perfor-

mance it is recommended to drive a value of 55h or FFh on these bits when not in XiP mode.

A 1-4-4 quad I/O read operation is shown in Figure 14. An example of this operation would be a Manufacturer/Device ID Read

(94h). Note that this type of transfer may contain one or more dummy bytes between the end of the address and the beginning

of the data output depending on the type of command and the operating frequency. See Table 17 for more information.

Figure 14: Quad I/O Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Read Operation

Command

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