AT25FF321A datasheet(20/119 Pages) DIALOG

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Datasheet

2021-08-19

DS-AT25FF321A-181

Revision J

AT25FF321A

32-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory

with Multi-I/O Support

4.4 QUAD OUTPUT OPERATION (1-1-4)

The AT25FF321A supports the Quad Output which enhances overall throughput over the standard SPI and dual operating modes

by increasing the data transfer rate. In this mode, data is transferred on four pins; SI, SO, WP, and HOLD. This means that only

1/4th the number of clocks are required to transfer the data relative to standard SPI mode. This is known as a 1-1-4 transfer which

is defined as: 1-pin command, 1-pin address, 4-pin data (1-1-4)

In Quad Output the command (C) and address (A) are driven to the memory device on the SI (IO0) pin. During write operations,

the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to inputs and the data is driven on all four pins, allowing four data

bits to be transferred on every clock. During read operations, once the command and address are transferred on the SI (IO0) pin,

the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to outputs and the data is driven on all four pins, allowing four

data bits to be transferred on every clock.

A 1-1-4 Quad Output read operation is shown in Figure 12. An example of this operation would be a Quad Output Read (6Bh).

Note that this type of transfer may contain one or more dummy bytes between the end of the address and the beginning of the

data output depending on the type of command and the operating frequency. See Table 17 for more information.

Figure 12: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Read Operation

A 1-1-4 Quad Output write operation is shown in Figure 13. An example of this operation would be a Quad Output Byte/Page

Program (32h).

Figure 13: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Write Operation

I/O0

(SI)

SCK

37 38

31 32

246

COMMAND

AAAA

AAA

XXXXXXXX

Address Bits A23-A0

DUMMY

DATA

OUT 1

DATA

OUT 2

DATA

OUT 3

DATA

OUT 4

DATA

OUT 5

I/O1

(SO)

High-impedance

D5 D1 D5 D1 D5 D1 D5 D1 D5 D1

I/O2

(WP)

High-impedance

D6 D2 D6 D2 D6 D2 D6 D2 D6 D2

I/O3

(HOLD)

MSB

High-impedance

D7 D3 D7 D3 D7 D3 D7 D3 D7 D3

D4 D0 D4 D0 D4 D0 D4 D0 D4 D0

I/O0

(SI)

SCK

37 38

31 32

COMMAND

AAAA

AAA

Address Bits A23-A0

I/O1

(SO)

High-impedance

I/O2

(WP)

High-impedance

I/O3

(HOLD)

High-impedance

DATA

IN 1

DATA

IN 2

DATA

IN 3

DATA

IN 4

DATA

IN 5

D5 D1 D5 D1 D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2 D6 D2 D6 D2

MSB

D7 D3 D7 D3 D7 D3 D7 D3 D7 D3

D4 D0 D4 D0 D4 D0 D4 D0 D4 D0

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