AT25FF321A datasheet(97/119 Pages) DIALOG

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Datasheet

2021-08-19

DS-AT25FF321A-181

Revision J

AT25FF321A

32-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory

with Multi-I/O Support

6.33 TERMINATE (F0H)

In some applications, it may be necessary to prematurely terminate a program or erase operation rather than wait for the program

or erase operation to complete normally. The Terminate command immediately aborts any operation in progress and returns the

device to an idle state.

Since the need to terminate the operation is immediate, the Write Enable command does not need to be issued prior to the

Terminate command. Therefore, the Terminate command operates independently of the state of the WEL bit in Status Register 1.

Once this command is issued, the operation in progress cannot be continued. To suspend and then continue an operation, use

the Program/Erase Suspend (75h) and Program/Erase Resume (7Ah) commands.

6.33.1 Command Prerequisites

The Terminate command can be executed only if the command has been enabled by setting the Reset Enabled (RSTE) bit in

Status Register 5 using the Write Status Register 5 command (71h + 05h address offset). This command must be executed before

the Terminate command is executed. If the Reset command has not been enabled (the RSTE bit in is cleared), then any attempt

at executing the Terminate command is ignored.

6.33.2 Transfer Format

The F0h command follows the 1-0-1 transfer format described in Section 4.2, where the command and data are transferred on

the SI pin. Immediately after the command is transferred, a confirmation data byte is transferred. This byte is required by the

hardware before the Terminate command can be executed. A timing diagram of this operation is shown in Figure 6.

6.33.3 Transfer Sequence

To perform device reset operation, the CS pin is asserted and the information transferred as follows:



The F0h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of

the command is transferred first.



The D0h confirmation byte is clocked into the device. Eight clocks are required to transfer the command. The most signifi-

cant bit of the command is transferred first. Note that is the confirmation byte is any value other than D0h, the entire com-

mand is ignored and the device returns to the idle state.



When the CS pin is deasserted after the D0h confirmation byte, the device initiates the terminate operation within a time of

tSWTERM. During the terminate sequence, no other command can be accepted by the device.

See Table 17 for more information on the transfer sequence for this command.

6.33.4 Programming Restrictions

The F0h Terminate command adheres to the following programming restrictions.



If a program or erase operation is in progress and cannot complete before the operation is terminated via the F0h com-

mand, the contents of the page being programmed or erased cannot be guaranteed to be valid.



The F0h command does not reset the device configuration registers in volatile mode. If a reset of the internal state is

desired, perform a 66h/99h command. This command resets the device and all programmable parameters and all volatile



The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and

returns to the standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power

cycle.

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