MPC8533EVJALGA datasheet(104/112 Pages) NXP

104 / 112 page

MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

104

Freescale Semiconductor

System Design Information

resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then,

Z0 =(RP +RN) ÷ 2.

Figure 63. Driver Impedance Measurement

Table 68 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,

nominal OVDD, 90°C.

21.8

Configuration Pin Muxing

The MPC8533E provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped

with an on-chip gated resistor of approximately 20 k

Ω. This value should permit the 4.7-kΩ resistor to pull

the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and

for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input

receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with

minimal signal quality or delay disruption. The default value for all configuration bits treated this way has

Table 68. Impedance Characteristics

Impedance

Local Bus, Ethernet, DUART,

Control, Configuration, Power

Management

PCI

DDR DRAM

Symbol

Unit

43 Target

25 Target

20 Target

43 Target

25 Target

20 Target

Note: Nominal supply voltages. See Table 1.

OVDD

OGND

Pad

Data

SW1

SW2

MPC8533EVJALGA Datasheet(PDF) 104 Page - NXP Semiconductors

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