SPC58NH84C3 datasheet(108/147 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC58EHx, SPC58NHx

108/147

DS12304 Rev 5

4.16.8

PSI5 timing

4.16.9

OctoSPI timing

4.16.9.1

OctoSPI mode

For SDR mode, below table is applied considering:

OERC for o/p pads are set as “11”

No delay module used for input clock

DQS being used as input clock. In case Clock Out being used as CLk In, frequency and

input timings would depend on memory characteristics and delay module might be

needed.

These timings are with OCTOSPI_DCR2.PRESCALAR = 1;

Table 61. PSI5 timing

Symbol

Parameter

Value

Unit

Min.

Max.

tMSG_DLY

Delay from last bit of frame (CRC0) to

assertion of new message received interrupt

—3

µs

tSYNC_DLY

Delay from internal sync pulse to sync pulse

trigger at the SDOUT_PSI5_n pin

tMSG_JIT

Delay jitter from last bit of frame (CRC0) to

assertion of new message received interrupt

cycle(1)

tSYNC_JIT

Delay jitter from internal sync pulse to sync

pulse trigger at the SDOUT_PSI5_n pin

±(1 PSI5_1µs_CLK +

1 PBRIDGEn_CLK)

cycle

1. Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.

Table 62. OctoSPI characteristics in SDR mode

Symbol

Parameter

Conditions

Value(1)

Unit

Min

Typ

Max

F(CLK)

OctoSPI clock frequency

2.7 V < VDD< 3.6 V Voltage

Range 1 CLOAD = 8 pF

——

100

MHz

tw(CKH)

OctoSPI clock high and

low time

—

tw(CKL)

—

ts(IN)

Data input setup time

—

0.5

—

th(IN)

Data input hold time

—

2.5

—

tv(OUT)

Data output valid time

—

th(OUT)

Data output hold time

—

-1(2)

——

1. Values in the table applies to Octal and Quad SPI mode.

2. This hold time is with respect to negative edge of CLKout.

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