SPC58NH84C3 datasheet(109/147 Pages) STMICROELECTRONICS

109 / 147 page

DS12304 Rev 5

109/147

SPC58EHx, SPC58NHx

Electrical characteristics

109

Figure 42. OctoSPI timing diagram - SDR mode

4.16.9.2

Hyperbus mode

The SPC58EHx, SPC58NHx microcontroller's OCTOSPI interface supports Hyperbus

memory devices with AC specifications compliant with

Hyperbus_Specification_Cypress_revF.pdf document (001-99253 Rev. *F, June 2017,

chapter 9.3 AC Characteristics). Note that:

•

Table 9.2 Clock Timing (on page 33 of this document) is valid if Freq <= 100 Mhz

•

Single Ended clock (no CK# signal)

•

Only 3.3 +/-10% voltage configuration

•

CS/RWDS/DQ/CK should be balanced on board

•

tDSS/tDSH specs not met by default. Internal delay module in SPC58EHx, SPC58NHx

microcontroller should be used by tuning OCTOSPI_DELAY_CFG and

OCTOSPI_DELAY_CTRL registers to achieve 1/12th cycle delay on DQS, to aid

correct data latching in OCTOSPI controller.

4.16.10

SDMMC timing

For SD SDIO modes, refer to AC specifications as in “SD Specifications Part 1 Physical

Layer Specification” document version 3.01, Feb. 2010, chapter “6.6 Bus Operating

Conditions for 3.3V Signaling”).

For eMMC mode, refer to AC specifications as in JEDEC standard “EMBEDDED MULTI-

MEDIA CARD (eMMC), ELECTRICAL STANDARD (4.5 Device)”, JESD84-B45, June 2011,

chapters “10.5 Bus timing” and “10.6 Bus timing for DAT signals during 2x data rate

operation”.

Note:

tIHddr and tIH input hold timing parameters minimum value is 1 ns.

SPC58NH84C3 Datasheet(PDF) 109 Page - STMicroelectronics