71M6543HT-IGTSLASHF datasheet(36/75 Pages) MAXIM

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Square Wave Output

The 71M654xT includes a square wave generator that

can be configured to present a square wave on the

SEGDIO15pin.Thissquarewavecanbeusedasaclock

to drive other devices and peripherals.

The output is enabled by setting the OUT_SQE bit. The

output frequency can then be selected by setting the

OUT_SQ[1:0] bits.

EEPROM Interface

The 71M654xT provides hardware support for both two-

pin (I2C) and three-wire (MICROWIRE) EEPROMs.

Two-Pin EEPROM Interface

The two-pin serial interface is multiplexed onto the

SEGDIO2 (SDCK) and SEGDIO3 (SDATA) pins. Configure

the interface for two-pin mode by setting DIO_EEX[1:0] =

01. The MPU communicates with the interface through

the SFR registers EEDATA and EECTRL. To write a

byte of data to the EEPROM the MPU places the data in

EEDATA and then writes the Transmit code to EECTRL.

This initiates the transmit operation which is finished

when the BUSY bit falls. INT5 is also asserted when

BUSY falls. The MPU can then check the RX_ACK bit to

see if the EEPROM acknowledged the transmission.

A byte is read by writing the Receive command to

EECTRL and waiting for the BUSY bit to fall. Upon com-

pletion, the received data is in EEDATA. The serial trans-

mit and receive clock is 78kHz during each transmission,

and then holds in a high state until the next transmission.

The two-pin interface handles protocol details. The MPU

can command the interface to issue a start, a repeated

start and a stop condition, and it can manage the transmit-

ted ACK status as well.

Three-Wire EEPROM Interface

The three-wire interface supports standard MICROWIRE

(single data pin with clock and select pins) or a subset of

SPI (separate DI and DO pins with clock and select pins).

MICROWIRE is selected by setting DIO_EEX[1:0] = 10.

In this mode, EECTRL selects whether the interface is

sending or receiving, and eight bits of data are transferred

in each transaction. In this configuration, SEGDIO2 is

configured for clock, and SEGDIO3 is configured for data.

When separate DI/DO pins are selected (DIO_EEX[1:0]

= 11) the interface operates as a subset of SPI. Only

SPI modes 0 or 3 are supported. In this configuration,

SEGDIO3 is DO and SEGDIO8 is DI.

UART

The 71M6543FT/HT/GT/GHT include a UART (UART0)

that can be programmed to communicate with a variety

of AMR modules and other external devices. A second

UART (UART1) is connected to the optical port.

The 80515 only supports two UARTs, but meters occasion-

ally need three. The 71M654xT tries to help in two ways.

First, as shown in Figure 7, the 71M654xT can be config-

ured to switch the optical UART to DIOs 5 and 17 by setting

UMUX_SEL (I/O RAM 0x2456[4]) to 1. This is useful when

a conventional UART can appear by command at different

pins. The DIOs must not be configured as LCD outputs.

Also, as shown in Figure 7, the 71M654xT can also be

configured to drive the opti7al UART with DIO signal in a

bit banged configuration. When control bit OPT_BB (I/O

RAM 0x2022[0]) is set, the optical port is driven by DIO5

and the SEGDIO5 pin is driven by UART1_TX. This con-

figuration is typically used when the two dedicated UARTs

must be connected to high speed clients and a slower

optical UART is permissible.

SPI Slave Port

The SPI slave port communicates directly with the MPU

data bus and is able to read and write Data RAM and

I/O RAM locations. It is also able to send commands to

the MPU. The interface to the slave port consists of the

SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These

pins are multiplexed with the combined DIO/LCD segment

driver pins SEGDIO36 to SEGDIO39.

Additionally, the SPI interface allows flash memory to

be read and to be programmed. To facilitate flash pro-

gramming, cycling power or asserting RESET causes

the SPI port pins to default to SPI mode. The SPI port is

disabled by clearing the SPI_E bit.

Possible applications for the SPI interface are:

• An external host reads data from CE locations to

obtain metering information. This can be used in

applications where the 71M654xT function as a smart

front-end with preprocessing capability. Since the

addresses are in 16-bit format, any type of XRAM data

can be accessed: CE, MPU, I/O RAM, but not SFRs or

the 80515-internal register bank.

• A communication link can be established via the SPI

interface: By writing into MPU memory locations, the

external host can initiate and control processes in the

71M654xT MPU. Writing to a CE or MPU location

normally generates an interrupt, a function that can be

71M6543HT-IGT/F Datasheet(PDF) 36 Page - Maxim Integrated Products

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