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R5F5671CDDFM Datasheet(PDF) 81 Page - Renesas Technology Corp

Part # R5F5671CDDFM
Description  120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,
PDF  178 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F5671CDDFM Datasheet(HTML) 81 Page - Renesas Technology Corp

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R01DS0373EJ0110 Rev.1.10
Page 81 of 178
Apr 15, 2022
RX671 Group
2. Electrical Characteristics
2.2
Recommended Operating Conditions
Note 1. Comply with the following potential condition: VCC = AVCC0 = AVCC1 = VCC_USB
Note 2. The low CL crystal unit cannot be used when the VBATT voltage is less than 2.0 V.
Note 3. For details, see section 50.6.11, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.
Note 4. The listed values apply when pins P30, P31, and P32 are set for the TAMPIn or RTCICn (n = 0 to 2) functions, and pin PJ3 is set
for the EXCIN function.
Note 5. The listed values apply when pins P12 and P13 are respectively set for the SCLHS0 and SDAHS0 functions in Hs-mode of the
RIICHS.
Note 1. Use a multilayer ceramic capacitor whose nominal capacitance is 0.22
μF and a capacitance tolerance is ±30% or better.
Table 2.2
Recommended Operating Conditions (1)
Item
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage*1
VCC
2.7
—
3.6
V
VSS
—
0
—
VBATT power supply voltage
VBATT
1.62*2
—3.6
V
USB power supply voltage
VCC_USB
—
VCC
—
V
VSS_USB
—
0
—
Analog power supply voltage*1, *3
AVCC0
—
VCC
—
V
AVSS0
—
0
—
AVCC1
—
VCC
—
AVSS1
—
0
—
VREFH0
2.7
—
AVCC0
VREFL0
—
0
—
Input voltage
Ports for 5 V tolerant: P12 to P17, P20,
P21, P30 to P33, P67, P73, PC0 to PC3,
and PJ3
Vin
–0.3
—
VCC + 3.6 (up to 5.5)
V
TAMPI0 to TAMPI2, RTCIC0 to RTCIC2,
EXCIN*4
–0.3
—
3.9
SCLHS0, SDAHS0*5
–0.3
—
VCC + 0.3
Port for 5 V tolerant: P07
–0.3
—
AVCC0 + 3.6 (up to 5.5)
P03, P05, P40 to P47
–0.3
—
AVCC0 + 0.3
Other than above
–0.3
—
VCC + 0.3
Operating
temperature
D version
Topr
–40
—
85
°C
G version
–40
—
105
Junction
temperature
D version
Tj
–40
—
105
°C
G version
–40
—
125
Table 2.3
Recommended Operating Conditions (2)
Item
Symbol
Value
Decoupling capacitance to stabilize the internal voltage
CVCL
0.22
μF ± 30%*1



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