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R5F5671CDDFM Datasheet(PDF) 166 Page - Renesas Technology Corp

Part # R5F5671CDDFM
Description  120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,
PDF  178 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F5671CDDFM Datasheet(HTML) 166 Page - Renesas Technology Corp

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R01DS0373EJ0110 Rev.1.10
Page 166 of 178
Apr 15, 2022
RX671 Group
2. Electrical Characteristics
2.13
Boundary Scan
Figure 2.102
Boundary Scan TCK Timing
Figure 2.103
Boundary Scan TRST# Timing
Table 2.63
Boundary Scan Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
TCK clock cycle time
tTCKcyc
100
—
—
ns
Figure 2.102
TCK clock high pulse width
tTCKH
45
—
—
ns
TCK clock low pulse width
tTCKL
45
—
—
ns
TCK clock rise time
tTCKr
——
5
ns
TCK clock fall time
tTCKf
——
5
ns
TRST# pulse width
tTRSTW
20
—
—
tTCKcyc
Figure 2.103
TMS setup time
tTMSS
20
—
—
ns
Figure 2.104
TMS hold time
tTMSH
20
—
—
ns
TDI setup time
tTDIS
20
—
—
ns
TDI hold time
tTDIH
20
—
—
ns
TDO data delay time
tTDOD
—
—
40
ns
TCK
tTCKcyc
tTCKH
tTCKf
tTCKL
tTCKr
RES#
TRST#
TCK
tTRSTW



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