L9788 datasheet(148/264 Pages) STMICROELECTRONICS

148 / 264 page

CAN FD interface

L9788

148/264

DS12308 Rev 4

12.2

CAN state diagram

Figure 67. CAN state diagram

GADG0912161302PS

CAN_STBY_ON

Trasmitter: Disabled

Receiver: Enabled

RXD:Wake-up/HIGH

BIAS OFF

CAN_RX

Trasmitter: Disabled

Receiver: Enabled

RXD:HIGH/BITSTREAM

msc_bit_can_rx_en 0/1(default 1)

BIAS ON

CAN_TRX

Trasmitter: Enabled

Receiver: Enabled

RXD:HIGH/BITSTREAM

msc_bit_can_rx_en 0/1(default 1)

BIAS ON

UCHIP-ON

CAN_STBY_OFF

Trasmitter: Disabled

Receiver: Disabled/Enabled

(msc_bit_wakeup_en 0/1)

RXD:no output

BIAS OFF

UCHIP-OFF

Uchip off

and

msc_can_auto_bias ='0'

msc_bit_wakeup_en = '0'

from any other state except CAN_STBY_ON

CAN_BIAS_OFF

Trasmitter: Disabled

Receiver: Enabled

RXD:no output

BIAS ON

CAN_BIAS_ON

Trasmitter: Disabled

Receiver: Enabled

RXD:Wake-up/HIGH

BIAS ON

msc_bit_auto_bias = '0'

Tsilence expired

msc_bit_wakeup_en = '1'

and

WU DETECTION

and

msc_bit_auto_bias = '1'

(WAKE_UP_CAN_DET_AUTO is latched)

msc_bit_can_en = '0'

(configure by MSC or

clear by reset matrix*13)

and

msc_bit_auto_bias = '1'

{msc_bit_can_en = '1'

and

(msc_bit_can_tx_en = '0'

inhibit = '1' (rst_matrix*10*12)

Dominant timeout = '1'

CAN_perm_recessive = '1'

RXDC perm_rec = '1'

VDD_CAN_OV = '1')}

msc_bit_can_en = '1'

and

msc_bit_can_tx_en = '1'

and

inhibit = '0' (rst matrix*10*12)

and

Dominant timeout = '0'

and

CAN_perm_recessive = '0'

and

RXDC perm_rec = '0'

and

VDD_CAN_OV = '0'

from any other state except CAN_STBY_ON

Uchip off

and

msc_can_auto_bias ='1'

Uchip off

Tsilence expired

NORMAL MODE

(MSC_BIT_CAN_EN =1)

msc_bit_can_en = '0'

(configure by MSC or

clear by reset matrix*13)

and

msc_bit_auto_bias = '0'

msc_bit_can_en = '0'

(configure by MSC or

clear by reset matrix*13)

and

msc_bit_auto_bias = '0'

msc_bit_can_en = '1'

and

msc_bit_can_tx_en = '1'

and

inhibit = '0' (rst matrix *10*12)

and

Dominant timeout = '0'

and

CAN_perm_recessive = '0'

and

RXDC perm_rec = '0'

and

VDD_CAN_OV = '0'

msc_bit_can_tx_en = '0'

inhibit = '1' (rst matrix *10*12)

Dominant timeout = '1'

CAN_perm_recessive = '1'

RXDC perm_rec = '1'

VDD_CAN_OV = '1'

msc_bit_can_tx_en = '1'

and

inhibit = '0' (rst matrix*10*12)

and

Dominant timeout = '0'

and

CAN_perm_recessive = '0'

and

RXDC perm_rec = '0'

and

VDD_CAN_OV = '0'

msc_bit_can_en = '0'

(configure by MSC or

clear by reset matrix*13)

and

msc_bit_auto_bias = '1'

{(msc_bit_wakeup_en = '1'

and

WU DETECTION)

Uchip on}

and

msc_bit_can_en = '1'

and

{msc_bit_can_tx_en = '0'

inhibit='1'(rst_matrix*10*12)

Dominant timeout = '1'

CAN_perm_recessive = '1'

RXDC perm_rec = '1'

VDD_CAN_OV = '1'}

{(msc_bit_wakeup_en = '1'

and

WU DETECTION)

Uchip on}

and

msc_bit_can_en = '1'

and

{msc_bit_can_tx_en = '0'

inhibit='1'(rst_matrix*10*12)

Dominant timeout = '1'

CAN_perm_recessive = '1'

RXDC perm_rec = '1'

VDD_CAN_OV = '1'}

{(msc_bit_wakeup_en = '1'

and

WU DETECTION)

Uchip on}

and

msc_bit_can_en = '0'

and

msc_bit_can_auto_bias = '0'

{(msc_bit_wakeup_en = '1'

and

WU DETECTION)

Uchip on}

and

msc_bit_can_en = '0'

and

msc_bit_can_auto_bias = '1'

{(msc_bit_wakeup_en = '1'

and

WU DETECTION)

Uchip on}

and

msc_bit_can_en = '0'

and

msc_bit_can_auto_bias = '1'

{msc_bit_can_en = '1'

and

(msc_bit_can_tx_en = '0'

inhibit = '1' (rst_matrix*10*12)

Dominant timeout = '1'

CAN_perm_recessive = '1'

RXDC perm_rec = '1'

VDD_CAN_OV = '1')}

LOW POWER MODE

(MSC_BIT_CAN_EN =0)

LOW POWER MODE

msc_bit_wakeup_en = '1'

and

WU DETECTION

and

msc_bit_auto_bias = '1'

(WAKE_UP_CAN_DET_AUTO is latched)

{(msc_bit_wakeup_en = '1'

and

WU DETECTION)

Uchip on}

and

msc_bit_can_en = '1'

and

{msc_bit_can_tx_en = '1'

and

inhibit='0'(rst_matrix*10*12)

and

Dominant timeout = '0'

and

CAN_perm_recessive = '0'

and

RXDC perm_rec = '0'

and

VDD_CAN_OV = '0'}

{(msc_bit_wakeup_en = '1'

and

WU DETECTION)

Uchip on}

and

msc_bit_can_en = '1'

and

{msc_bit_can_tx_en = '1'

and

inhibit='0'(rst_matrix*10*12)

and

Dominant timeout = '0'

and

CAN_perm_recessive = '0'

and

RXDC perm_rec = '0'

and

VDD_CAN_OV = '0'}

CAN register reset defaut values on POR VBSTBY

MSC_BIT_CAN_TX_EN = 1

MSC_BIT_CAN_RX_EN = 1

MSC_BIT_CAN_EN = 1

MSC_CAN_TXD_DOM_EN = 1

MSC_CAN_PERM_REC_EN= 1

MSC_CAN_PERM_DOM_EN= 1

MSC_CAN_RXD_REC_EN=1

MSC_CAN_AUTO_BIAS = 1

CAN register masked with RSTN = 0

Trasmitter disabled

(MSC_BIT_CAN_TX_EN = 0)

Diagnostics disabled

(MSC_CAN_TXD_DOM_EN = 0

MSC_CAN_PERM_REC_EN= 0

MSC_CAN_PERM_DOM_EN= 0

MSC_CAN_RXD_REC_EN=0)

L9788 Datasheet(PDF) 148 Page - STMicroelectronics

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