L9788 datasheet(150/264 Pages) STMICROELECTRONICS

150 / 264 page

CAN FD interface

L9788

150/264

DS12308 Rev 4

CAN transceiver is in normal mode, the transmitter is disabled and its state changes to

CAN_RX in case of at least one of the following events:



Dominant TxDC time out and CAN_TXD_DOM_EN MSC bit = 1;



CAN permanent recessive CAN_PERM_REC_EN MSC bit = 1;



RxDC permanent recessive CAN_RXD_REC_EN MSC bit = 1;



VDD_CAN overvoltage detection (MSC bit VDD_CAN_OV = 1);



VDD_CAN undervoltage detection active;



MSC bit CAN_TX_EN = 0;



Reset matrix Conditions *10*12 (see Reset Matrix section).

The CAN receiver is not disabled in case of any failure condition.

The device provides the following 4 error handling features; the CAN error handling function

can be disabled by setting the dedicated corresponding MSC bit. The error handling must

be also enabled by setting the CAN_EN bit MSC_CONFIG-REG17-1[2].

12.6.1

Dominant CAN_TX time out

If CAN_TX is in dominant state (low) for t > tTXDC_DOM_TO the transmitter will be disabled,

CAN_TXD_DOM status bit will be latched and can be read and cleared by MSC. The

transmitter remains disabled until the status register is cleared or until the state returns

recessive according to the setting of the bit CAN_TX_DOM_ERR_CFG MSC CONFIG-

REG21 [0]. The detection of this error is enabled by the CAN_TXD_DOM_EN bit

MSC_CONFIG_REG21[3] and by the CAN_TX_EN bit MSC_CONFIG_REG17_1[3].

12.6.2

CAN permanent recessive

If CAN_TX changes to dominant (low) state but CAN bus does not follow for 4 times, the

transmitter will be disabled, CAN_PERM_REC status bit will be latched and can be read

and cleared by MSC. The transmitter remains disabled until the status register is cleared.

The detection of this error is enabled by the CAN_PERM_REC_EN bit

MSC_CONFIG_REG21[4] and by the CAN_TX_EN bit MSC_CONFIG_REG17_1[3].

12.6.3

CAN permanent dominant

If the bus state is dominant (low) for t > tdom a permanent dominant status will be detected.

CAN_PERM_DOM status bit is latched and can be read and cleared by MSC. The

transmitter will not be disabled. The detection of this error is enabled by the

CAN_PERM_DOM_EN bit MSC_CONFIG_REG21[5].

12.6.4

CAN_RX permanent recessive

If CAN_RX Pin is clamped to recessive (high) state, the controller is not able to recognize a

bus dominant state and could start messages at any time, which results in disturbing the

overall bus communication. Therefore, if CAN_RX does not follow CAN_TX for 4 times the

transmitter will be disabled. CAN_RXD_REC status bit will be latched and can be read and

cleared by MSC. The transmitter remains disabled until the status register is cleared. The

detection of this error is enabled by the CAN_RXD_REC_EN bit MSC_CONFIG_REG21[6]

and by the CAN_TX_EN bit MSC_CONFIG_REG17_1[3].

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