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L9788 Datasheet(PDF) 167 Page - STMicroelectronics |
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L9788 Datasheet(HTML) 167 Page - STMicroelectronics |
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167 / 264 page  DS12308 Rev 4 167/264 L9788 LIN/K-LINE interface 263 tLIN1 (Time Out) LIN permanent recessive -30 40 50 µs LIN tLIN2 LIN permanent dominant - 9 12 15 ms LIN ViD_LIN Input voltage for dominant state Application information - - 0.4 VB_IN V LIN(Bus Receiver) Vth_DOM Input voltage for dominant threshold Application information 0.4 VB_IN 0.45 VB_IN 0.5 VB_IN V LIN(Bus Receiver) ViR_LIN Input voltage for recessive state - 0.6 VB_IN - VB_IN V LIN(Bus Receiver) Vth_REC Input voltage for recessive threshold - 0.5 VB_IN 0.55 VB_IN 0.6 VB_IN V LIN(Bus Receiver) Vth_CNT = (Vth_REC + Vth_DOM) / 2 Input receiver tolerance center voltage - 0.475 VB_IN 0.5 VB_IN 0.525 VB_IN V LIN(Bus Receiver) Vth_HYS = Vth_REC - Vth_DOM Input voltage hysteresis voltage - 0.07 VB_IN 0.1 VB_IN 0.175 VB_IN V LIN(Bus Receiver) tdly(LIN)HL Output delay time HtoL Cbus = 10 nF, Pull up = 500 Ω -- 50 µs LIN(Bus Receiver) tdly(LIN)LH Output delay time LtoH Cbus = 10 nF, Pull up = 500 Ω -- 50 µs LIN(Bus Receiver) tDLY_HL Input delay time HtoL CRXD=20pF - - 6 µs LIN(Bus Receiver) tDLY_LH Input delay time LtoH CRXD=20pF - - 6 µs LIN(Bus Receiver) tDLY Input delay time tDLY_HL- tDLY_LH -2 - 2 µs LIN(Bus Receiver) D1 Duty Cycle Thresmax = 0.744VB_IN, Thdommax = 0.581VB_IN, VB_IN = 7-18 V, tbit = 50 µs, D1 = tbus_resmin/(2xtbit) 0.396 - - - LIN(Bus Receiver) D2 Duty Cycle Thresmin = 0.422VB_IN, Thdommin = 0.284VB_IN, VB_IN = 7.6-18V, tbit = 50 µs, D2 = tbus_resmax/(2xtbit) - - 0.581 - LIN(Bus Receiver) D3 Duty Cycle Thresmax = 0.778VB_IN, Thdommax = 0.616VB_IN, VB_IN = 7-18 V, tbit = 96 µs, d3 = tbus_resmin/(2xtbit) 0.417 - - - LIN(Bus Receiver) Table 82. Electrical characteristics of LIN interface (continued) Symbol Parameter Test condition Min Typ Max Unit Pin |
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