L9788 datasheet(178/264 Pages) STMICROELECTRONICS

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Micro second channel (MSC) interface

L9788

178/264

DS12308 Rev 4

The MSC is used to receive the input command and data from CPU and to transmit an

output data to CPU. Four signals are used according to the timing chart of Figure 81:

EN: Bus Enable

There is one input for chip select at pin [EN] This signal is LVTTL Interface from Master to

Slave. MSC uses inverted polarity for EN: a logic '1' is a 'passive level' and a logic '0' is a

'active level'. It is possible to drive multiple power devices with shared CL and DI lines and

individual EN signal.

CL: Synchronous Serial Clock

The clock pins are [CLP] and [CLN], the differential clock. [CLP]-[CLN] is referred to as CL.

The maximum downstream clock rate is CL= 35 MHz.There is an internal resistor between

pins [CLP] and [CLN].This signals are LVDS Interface from Master to Slave.

DI: Serial Input Data

Differential inputs for downstream data are pins [DIP] and [DIN]; the differential input signal

[DIP]-[DIN] is referred to as DI. There is an internal resistor between pins [DIPP] and [DIN].

These signals are LVDS Interface from Master to Slave

DO: Serial Output Data

There is one push-pull output for upstream data at pin [DO]. Upstream is done with a lower

clock rate fDO, selectable by the microcontroller; after a reset the upstream clock rate is fDO

= fCL/32.The upstream clock is synchronous with CL since it is derived from a clock

divider.Therefore the CL signal must be always running independently whether a

downstream transmission is running or not.This signal is LVTTL Interface from Slave to

Master.

tENsetup

EN setup time (i.e. time

between falling edge of EN and

next falling edge of CK)

Tested by SCAN/

tENhold

EN hold time (i.e. time between

falling edge of CK and next

rising edge of EN)

Tested by SCAN/

tSDO /tCK

Data out cycle time F_DO_SEL

(CONFIG_REG2 [1:2]) = “11”

F_DO_SEL = “10” F_DO_SEL

= “01” F_DO_SEL = “00”

Tested by SCAN/

128

fCK

Clock range at CK as long as

there is a clock at pins

MSC_CK_P,



MSC_CK_N. tCPP ≥ 2 * tCL

Tested by SCAN/

MHz

Clock range at CK as long as

there is a clock at pins

MSC_CK_P,



MSC_CK_N. tCPP ≥ 4 * tCL

Tested by SCAN/

MHz

tSDOdelay

Tested by SCAN/

160

Table 85. MSC communication timing parameters (continued)

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

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