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L9788 Datasheet(PDF) 181 Page - STMicroelectronics

Part # L9788
Description  Multifunction IC for automotive engine management system
PDF  264 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9788 Datasheet(HTML) 181 Page - STMicroelectronics

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DS12308 Rev 4
181/264
L9788
Micro second channel (MSC) interface
263
18.2
Downstream communication
The enable input is active with inverted polarity - i.e. ‘low level' during the active phases of
command or data frames. An active enable signal validates the DI input signal. Outside the
active phase (enable line is at high level) invalid data may occur at DI. The active phase of a
downstream frame starts with the falling edge of the enable signal and ends with the rising
edge of the enable signal. The enable signal changes its state with the rising edge of the
clock CL. DI changes its state on rising edge and it is latched by L9788 on the falling edge of
CL. Downstream frames are synchronous serial frames. They support enable signal and
command/data selection bit as part of the frame. Command/data selection bit allows
distinguishing frames as command and data frames in the receiver circuit. Command
frames and data frames may be sent in any sequence with a passive phase of at least 2 CL-
cycles after each frame.
18.2.1
Command frame
A command frame always starts with a high level bit (command selection bit). The number
of the command bit of the active phase of a command frame NCB is fixed to 16. If the
number of the command bit is not equal to NCB = 16 the frame will be ignored, the
command will not be executed and the error flag (TRANS_L) will be set. If the MSC
command frame has an invalid command the flag "CMD_ERROR" is set but no action on
outputs is taken. The command frame is ignored.
The length of the command frame's passive phase tCPP must be a minimum of 2 * tCL.
VDI_low
Differential input low
detection level
VDI_low= VDI_P_low-
VDI_N_low
--100
-
-
mV
MSC_DI_P
MSC_DI_N
VDO_L
DO output low level
VDDIO=5V or 3.3V
Isink current=2mA
-
-
0.5
V
MSC_DO
VDO_H
DO output high level
VDDIO =5V or 3.3V
Isink current=2mA
VDDIO
-0.5
--
V
MSC_DO
fDO
Maximum frequency
Tested by SCAN
fCK/128 fCK/64 fCK/16 MHz
MSC_DO
ENL
Low input level
-
-0.3
-
1.1
V
MSC_EN
ENH
High input level
-
2.3
-
VDD5
+0.3
VMSC_EN
VHYST
Hysteresis
-
0.1
-
V
MSC_EN
IIN
Input current
-
-
32
μA
MSC_EN
RPU
Pull up resistor
-
50
-
250
kΩ
MSC_EN
Table 86. MSC electrical characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Pin



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