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L9788 Datasheet(PDF) 212 Page - STMicroelectronics |
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L9788 Datasheet(HTML) 212 Page - STMicroelectronics |
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212 / 264 page ![]() Micro second channel (MSC) interface L9788 212/264 DS12308 Rev 4 18.5.19 CONFIG-REG 20 [7] PDRV_O2H_DLY Selection of delay time for switching from low to high current in predriver on/off transitions in o2h configuration. 0: 150µs selected (default) 1: 300µs selected [6] LIN_TX_DOM_ERR_CFG LIN Tx enable after dominant error timeout: 0: re-enable as soon as Tx become recessive (default) 1: wait for error flag read [5] CAN_TDI CAN transmission depends on WDA: 0: WDA does not affect CAN (default) 1: disable transmission if WDA_INT active [4] CAN_LOOP_EN CAN looping mode enable: 0: disable (default) 1: enable [3] KEY_OC_RETRY_MAX_EN Enable a maximum number of retry after OVC, when wake up by key: C 0 C 1 C 2 C 3 C 4 C 5 C 6 D0 D1 D2 D3 D4 D5 D6 D7 CONFIG- REG 20 1 1 1 1 1 1 0 BIST_ EN FIN_ WAK E WAKE_ UP_TIM ER_EN _SEL KEY_OC _RETRY _MAX_E N CAN_LO OP_EN CAN_T DI LIN_TX_ DOM_E RR_CFG PDRV_O 2H_DLY RW DEFAULT 0 0 0 0 0 0 0 0 RESET SOURCE D0:D1; D4:D7 v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset, after_run_reset, RSTN_IN D2:D3 the read bits are from satellite logic on VB_STBY and are not affected by reset matrix ACTIVATION D0 bit active as pulse D1:D7 bits active as level CONTROL ACCESS D0:D3 not locked bits D4:D7 locked bits |
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