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L9788 Datasheet(PDF) 213 Page - STMicroelectronics |
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L9788 Datasheet(HTML) 213 Page - STMicroelectronics |
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213 / 264 page ![]() DS12308 Rev 4 213/264 L9788 Micro second channel (MSC) interface 263 0: disable (default) 1: enable Bits going to Wake Up Timer Logic [2] WAKE_UP_TIMER_EN_SEL Select the source of activation for the wake_up_timer 0: from MSC start/stop commands (default) 1: from KEY_IN 1->0 Bits going to Wake Up Timer Logic [1] FIN_WAKE 0: satellite logics execute auto clear 1 second after power up (default) 1: micro confirmed power up, no auto clear after 1 second [0] BIST_EN Bist enable for regulators 0: disable (default) 1: enable 18.5.20 CONFIG-REG 21 [7] CAN_AUTO_BIAS 0: auto biasing disabled 1: auto biasing enabled (default) [6] CAN_RXD_REC_EN 0: error handling disable C 0 C 1 C 2 C 3 C 4 C 5 C 6 D0 D1 D2 D3 D4 D5 D6 D7 CONFIG -REG 21 0 0 0 0 0 0 1 CAN_TX _DOM_E RR_CFG OL_RED BUCK _SLO W_SR CAN_T XD_DO M _EN CAN_PE RM_RE C_EN CAN_ PERM _DOM _EN CAN_ RXD_ REC_ EN CAN_A UTO_BI AS RW DEFAULT 0 0 0 1 1 1 1 1 ACTIVATION D0:D2 v3v3a_ov, v3v3a_uv, v3v3d_ov, v3v3d_uv, vdd5_uv, vddio_uv, sw_reset, after_run_reset, RSTN_IN D3:D7 the read bits are from satellite logic on VB_STBY and are not affected by reset matrix CONTROL ACCESS D0:D7 bits active as level RESET SOURCE D0 locked bit D1:D7 not locked bits |
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