LSM6DSTX datasheet(112/175 Pages) STMICROELECTRONICS

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13.17

MLC_STATUS (15h)

Machine learning core status register (R)

Table 259. MLC_STATUS register

IS_MLC8

IS_MLC7

IS_MLC6

IS_MLC5

IS_MLC4

IS_MLC3

IS_MLC2

IS_MLC1

Table 260. MLC_STATUS register description

IS_MLC8

Interrupt status bit for MLC8 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC7

Interrupt status bit for MLC7 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC6

Interrupt status bit for MLC6 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC5

Interrupt status bit for MLC5 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC4

Interrupt status bit for MLC4 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC3

Interrupt status bit for MLC3 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC2

Interrupt status bit for MLC2 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC1

Interrupt status bit for MLC1 interrupt event. (1: interrupt detected; 0: no interrupt)

13.18

PAGE_RW (17h)

Enable read and write mode of advanced features dedicated page (R/W)

Table 261. PAGE_RW register

EMB_

FUNC_LIR

PAGE_

WRITE

PAGE_

READ

0(1)

1. This bit must be set to 0 for the correct operation of the device.

Table 262. PAGE_RW register description

EMB_FUNC_LIR

Latched interrupt mode for embedded functions. Default value: 0

(0: embedded functions interrupt request not latched;

1: embedded functions interrupt request latched)

PAGE_WRITE

Enable writes to the selected advanced features dedicated page(1). Default value: 0

(1: enable; 0: disable)

PAGE_READ

Enable reads from the selected advanced features dedicated page(1). Default value: 0

(1: enable; 0: disable)

1. Page selected by PAGE_SEL[3:0] in PAGE_SEL (02h) register

LSM6DSTX

MLC_STATUS (15h)

DS14039 - Rev 1

page 112/175

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