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PLM5177DCPR Datasheet(PDF) 32 Page - Texas Instruments |
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PLM5177DCPR Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 54 page ![]() The f(SW) synchronization stops if the device enters power save mode or μSleep operation, if enabled. Once the converter enters the PWM operation again, the device re-syncs to a pin signal. The synchronization timings are given in Figure 8-18. VT(SYNC) RT OSC PLL BB CORE LOGIC + ± SYNC SYNC ACTIVITY DETECTION LIMITER Figure 8-17. Main Oscillator Functional Block Diagram V(SYNC) VT+(SYNC) PLL lock Cycles VT-(SYNC) td(Det,Sync) RT pro gramed fsw td(Det,Sync) fsw Synced RT pro gramed fsw Figure 8-18. Timing Diagram SYNC Function The sync pin has a dual function to configure the current limit direction. 8.4 Device Functional Modes Figure 8-19 describes the functional behavior of the internal device logic. LM5177 SNVSBU4A – JUNE 2022 – REVISED OCTOBER 2022 www.ti.com 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5177 |
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