PLM5177DCPR datasheet(4/54 Pages) TI

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Table 5-1. Pin Functions (continued)

Type(1)

Description

Name

No.

EN/UVLO

Enable pin. The pin enables or disables the device. If the pin is less than 0.6 V, the device shuts

down. The pin must be raised above 0.65 V to enable the device. This pin is the enable pin for the

device internal reference circuit and input voltage UVLO comparator input.

Feedback pin for output voltage regulation. Connect a resistor divider network from the output of

the converter to the FB pin. Connect the FB pin to VCC to operate at a fixed output voltage of 12

HB1

Bootstrap supply pin for buck half-bridge. An external capacitor is required between the HB1 pin

and the SW1 pin, respectively, to provide bias to the high-side MOSFET gate driver.

HO1

High-side gate driver output for the buck half-bridge

HB2

Bootstrap supply pin for boost half-bridge. An external capacitor is required between the HB2 pin

and the SW2 pin, respectively, to provide bias to the high-side MOSFET gate driver.

HO2

High-side gate driver output for the boost half-bridge

IMONOUT

Current monitor output pin. Output of the voltage-controlled current source of the optional current

monitor. Connect the pin to a resistor to sense the voltage across. If the output or input current

sense amplifier is configured as current limiter, an external RC network connected between

IMONOUT and AGND compensates the regulator of the current feedback loop. Connect the

IMONOUT pin to VCC to disable the block and reduce the quiescent current.

ISNSN

Positive sense input of the output or input current sense amplifier. An optional current sense

resistor connected between ISNSN and ISNSP can be located either on the input side or on the

output side of the power stage.

ISNSP

Negative sense input of the output or input current sense amplifier. An optional current sense

resistor connected between ISNSN and ISNSP can be located either on the input side or on the

output side of the power stage.

LO1

Low-side gate driver output for the buck half-bridge

LO2

Low-side gate driver output for the boost half-bridge

MODE

Digital input to select device operation mode. If the pin is pulled low, power save mode (PSM) is

enabled. If the pin is pulled high, the forced PWM or CCM operation is enabled. The configuration

can be changed dynamically during operation. Do not leave this pin floating. If this function is not

used, connect the pin to VCC or GND.

No internal connection

Make no external connection

nFLT

Open-drain output pin for fault indication or power good. This pin is pulled low when FB is outside

a ±10% regulation window around the regulation window of the nominal output voltage.

PowerPAD

PAD

Connect the PowerPAD to the analog ground. Use thermal vias to connect to a PCB ground plane

for improved power dissipation.

PGND

Power ground. This pin is the high current ground connection to the low-side gate drivers and for

the internal VCC regulator.

I/O

Switching frequency programming pin. An external resistor is connected to the RT pin and AGND

to set the switching frequency.

SLOPE

A resistor connected between the SLOPE pin and AGND provides the slope compensation ramp

for stable current mode operation in both buck and boost mode.

SS/ATRK

I/O

Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start

time. Analog output voltage tracking pin. The VOUT regulation target can be programmed

by connecting the pin to variable voltage reference (for example, through a digital to analog

converter). The internal circuit selects the lowest voltage applied to the pin.

SW1

Inductor switch node for the buck half-bridge

LM5177

SNVSBU4A – JUNE 2022 – REVISED OCTOBER 2022

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