PT7313E

V1.0

5

February 2010

CONTROL BUS SPECIFICATION

BUS INTERFACE

All functions of the PT7313E are controlled by the I

2C interface, the interface is consisting by SDA and SCL pins. Detail

protocol of the I

2C bus will discuss on the next section. It should be noted that the bus level pull-up resistors connected to

the PT7313E positive supply voltage may required in some application especially the MCU output high level is no

enough.

DATA VALIDITY

A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW

State of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below.

START AND STOP CONDITIONS

A Start Condition is activated when

1) The SCL is set to HIGH and

2) SDA shifts from HIGH to LOW State.

The Stop Condition is activated when

1) SCL is set to HIGH and

2) SDA shifts from LOW to HIGH State. Please refer to the timing diagram below..

BYTE FORMAT

Every byte transmitted to the SDA Line consists of 8 bits. Each byte must be followed by an Acknowledge Bit. The MSB

is first transmitted.