PT7313E

V1.0

7

February 2010

DATA BYTES

MSB

LSB

Function

0

0

B2

B1

B0

A2

A1

A0

Master Volume

1

1

0

B1

B0

A2

A1

A0

Speaker ATT LR

1

1

1

B1

B0

A2

A1

A0

Speaker ATT RR

1

0

0

B1

B0

A2

A1

A0

Speaker ATT LF

1

0

1

B1

B0

A2

A1

A0

Speaker ATT RF

0

1

0

G1

G0

LD

S1

S0

Input Switch and Gain

0

1

1

0

C3

C2

C1

C0

Bass Control

0

1

1

1

C3

C2

C1

C0

Treble Control

DATA RATE

The PT7313E support Standard-Mode (100kbit/s) I

2C data rate In all operation condition, in specified condition it also

support Fast-Mode (400kbit/s) I

2C data rate, please refer to the follow table:

MCU Level

PT7313E VDD Voltage

4V

5V

6V

7V

8V

9V

10V

2.5V

F

F

x

x

x

x

x

3.3V

F

F

F

F

S

S

x

5V

x

F

F

F

F

F

F

Notes:

1. x = Not allow in this combination; S = Standard Mode Supported, F = Fast Mode Supported.

2. Data rate specification is design guarantee only, not fully tested in every combination.

I2C BUS INITIAL TIME

The PT7313E is controlled by the I

2C bus command; each time the supply voltage applied to chip it needs an initial time

to reset all of the internal decoder register, in this period access the I

2C bus is prohibited. The initial time is determinate

by capacitance it attached on REF pin (CREF) and Td. For proper operation USER must check the I

2C starts timing is fit

this requirement and recommended Td timing shown on next page is 50mS.

VDD

VREF

I2C

90% VREF

I2C PROHIBIT

Td

POWER ON

I2C STARTS

50mS