operation. The WD-EN pin can be toggled any time during the device operation. The Figure 8-7 diagram shows

timing behavior with WD-EN pin control.

VDD

WDI

ttWDt

ttWDOt

VPOR

Ignore

WD-EN

ttWDt

tWD

Ignore

WDO

Figure 8-7. Watchdog Enable: WD-EN Pin Control

SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and

SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during

watchdog operation. Refer Section 8.3.1.4 section for additional details regarding SET[1:0] pin behavior.

A pinout which does not offer WD-EN or SET[1:0] pins uses WDI float pin status to disable the watchdog

operation. Users can float the WDI pin during normal operation to disable the watchdog. To enable watchdog,

drive the WDI pin and apply a valid edge to trigger the watchdog. It is recommended to drive HIGH and then

LOW when exiting the WDI float state.

Pinout options A, B, K offer watchdog timer control using a capacitance connected between CWD and GND

pin. A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting

disabled. Note, capacitance value is detected and latched during start-up or after an error event. Changing

capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to

detect change in capacitance.

When watchdog is disabled the ongoing frame will be terminated and WDO will stay deasserted. When enabled

the device will immediately enter tWD frame and start watchdog monitoring operation.

8.3.1.3 tSD Watchdog Start Up Delay

The TPS3435 supports watchdog startup delay feature. This feature is activated after power up or after WDO

assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted.

This feature allows time for the host complete boot process before watchdog monitoring can take over. The start

up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the

device part number selected. Refer Section 5 section for details to map the part number to tSD time. Pinout

option A, B, K are available only in no delay or 10 sec start up delay options.

The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on

the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD

frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI

pin triggers the watchdog error by asserting the WDO output pin.

The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or

WDI float functionality as described in Section 8.3.1.2 section.

Figure 8-8 diagram shows the operation for tSD time frame.

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TPS3435

SNVSCF7 – DECEMBER 2022

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